1 // Copyright 2012-2013 The Rust Project Developers. See the COPYRIGHT
2 // file at the top-level directory of this distribution and at
3 // http://rust-lang.org/COPYRIGHT.
5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
8 // option. This file may not be copied, modified, or distributed
9 // except according to those terms.
11 // The classification code for the x86_64 ABI is taken from the clay language
12 // https://github.com/jckarter/clay/blob/master/compiler/src/externals.cpp
14 use abi::{ArgType, ArgAttribute, CastTarget, FnType, LayoutExt, Reg, RegKind};
15 use context::CrateContext;
17 use rustc::ty::layout::{self, Layout, TyLayout, Size};
19 #[derive(Clone, Copy, PartialEq, Debug)]
27 #[derive(Clone, Copy, Debug)]
30 // Currently supported vector size (AVX).
31 const LARGEST_VECTOR_SIZE: usize = 256;
32 const MAX_EIGHTBYTES: usize = LARGEST_VECTOR_SIZE / 64;
34 fn classify_arg<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>, arg: &ArgType<'tcx>)
35 -> Result<[Class; MAX_EIGHTBYTES], Memory> {
36 fn unify(cls: &mut [Class],
39 let i = (off / 8) as usize;
40 let to_write = match (cls[i], c) {
41 (Class::None, _) => c,
42 (_, Class::None) => return,
45 (_, Class::Int) => Class::Int,
48 (_, Class::Sse) => Class::Sse,
50 (Class::SseUp, Class::SseUp) => Class::SseUp
55 fn classify<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>,
56 layout: TyLayout<'tcx>,
59 -> Result<(), Memory> {
60 if off % layout.align(ccx).abi() != 0 {
61 if layout.size(ccx).bytes() > 0 {
68 Layout::Scalar { value, .. } |
69 Layout::RawNullablePointer { value, .. } => {
70 let reg = match value {
72 layout::Pointer => Class::Int,
74 layout::F64 => Class::Sse
79 Layout::CEnum { .. } => {
80 unify(cls, off, Class::Int);
83 Layout::Vector { element, count } => {
84 unify(cls, off, Class::Sse);
86 // everything after the first one is the upper
87 // half of a register.
88 let eltsz = element.size(ccx).bytes();
90 unify(cls, off + i * eltsz, Class::SseUp);
94 Layout::Array { count, .. } => {
96 let elt = layout.field(ccx, 0);
97 let eltsz = elt.size(ccx).bytes();
99 classify(ccx, elt, cls, off + i * eltsz)?;
104 Layout::Univariant { ref variant, .. } => {
105 for i in 0..layout.field_count() {
106 let field_off = off + variant.offsets[i].bytes();
107 classify(ccx, layout.field(ccx, i), cls, field_off)?;
111 Layout::UntaggedUnion { .. } => {
112 for i in 0..layout.field_count() {
113 classify(ccx, layout.field(ccx, i), cls, off)?;
117 Layout::FatPointer { .. } |
118 Layout::General { .. } |
119 Layout::StructWrappedNullablePointer { .. } => return Err(Memory)
125 let n = ((arg.layout.size(ccx).bytes() + 7) / 8) as usize;
126 if n > MAX_EIGHTBYTES {
130 let mut cls = [Class::None; MAX_EIGHTBYTES];
131 classify(ccx, arg.layout, &mut cls, 0)?;
133 if cls[0] != Class::Sse {
136 if cls[1..n].iter().any(|&c| c != Class::SseUp) {
142 if cls[i] == Class::SseUp {
144 } else if cls[i] == Class::Sse {
146 while i != n && cls[i] == Class::SseUp { i += 1; }
156 fn reg_component(cls: &[Class], i: &mut usize, size: u64) -> Option<Reg> {
174 let vec_len = 1 + cls[*i+1..].iter().take_while(|&&c| c == Class::SseUp).count();
176 Some(if vec_len == 1 {
183 kind: RegKind::Vector,
184 size: Size::from_bytes(vec_len as u64 * 8)
188 c => bug!("reg_component: unhandled class {:?}", c)
192 fn cast_target(cls: &[Class], size: u64) -> CastTarget {
194 let lo = reg_component(cls, &mut i, size).unwrap();
195 let offset = i as u64 * 8;
196 let target = if size <= offset {
199 let hi = reg_component(cls, &mut i, size - offset).unwrap();
200 CastTarget::Pair(lo, hi)
202 assert_eq!(reg_component(cls, &mut i, 0), None);
206 pub fn compute_abi_info<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>, fty: &mut FnType<'tcx>) {
207 let mut int_regs = 6; // RDI, RSI, RDX, RCX, R8, R9
208 let mut sse_regs = 8; // XMM0-7
210 let mut x86_64_ty = |arg: &mut ArgType<'tcx>, is_arg: bool| {
211 let cls = classify_arg(ccx, arg);
213 let mut needed_int = 0;
214 let mut needed_sse = 0;
215 let in_mem = match cls {
217 Ok(ref cls) if is_arg => {
220 Class::Int => needed_int += 1,
221 Class::Sse => needed_sse += 1,
225 arg.layout.is_aggregate() &&
226 (int_regs < needed_int || sse_regs < needed_sse)
232 arg.make_indirect(ccx);
234 arg.attrs.set(ArgAttribute::ByVal);
236 // `sret` parameter thus one less integer register available
240 // split into sized chunks passed individually
241 int_regs -= needed_int;
242 sse_regs -= needed_sse;
244 if arg.layout.is_aggregate() {
245 let size = arg.layout.size(ccx).bytes();
246 arg.cast_to(ccx, cast_target(cls.as_ref().unwrap(), size))
248 arg.extend_integer_width_to(32);
253 if !fty.ret.is_ignore() {
254 x86_64_ty(&mut fty.ret, false);
257 for arg in &mut fty.args {
258 if arg.is_ignore() { continue; }
259 x86_64_ty(arg, true);