src/librustc_platform_intrinsics/hexagon.rs

   1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
   2 // file at the top-level directory of this distribution and at
   3 // http://rust-lang.org/COPYRIGHT.
   4 //
   5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
   6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
   7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
   8 // option. This file may not be copied, modified, or distributed
   9 // except according to those terms.
  10
  11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
  12 // ignore-tidy-linelength
  13
  14 #![allow(unused_imports)]
  15
  16 use {Intrinsic, Type};
  17 use IntrinsicDef::Named;
  18
  19 pub fn find(name: &str) -> Option<Intrinsic> {
  20     if !name.starts_with("Q6_") { return None }
  21     Some(match &name["Q6_".len()..] {
  22         "R_vextract64" => Intrinsic {
  23             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32]; &INPUTS },
  24             output: &::U32,
  25             definition: Named("llvm.hexagon.V6.extractw")
  26         },
  27         "R_vextract128" => Intrinsic {
  28             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32]; &INPUTS },
  29             output: &::U32,
  30             definition: Named("llvm.hexagon.V6.extractw.128B")
  31         },
  32         "V_lo64" => Intrinsic {
  33             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS },
  34             output: &::U32x16,
  35             definition: Named("llvm.hexagon.V6.lo")
  36         },
  37         "V_lo128" => Intrinsic {
  38             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS },
  39             output: &::U32x32,
  40             definition: Named("llvm.hexagon.V6.lo.128B")
  41         },
  42         "V_hi64" => Intrinsic {
  43             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS },
  44             output: &::U32x16,
  45             definition: Named("llvm.hexagon.V6.hi")
  46         },
  47         "V_hi128" => Intrinsic {
  48             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS },
  49             output: &::U32x32,
  50             definition: Named("llvm.hexagon.V6.hi.128B")
  51         },
  52         "V_vsplat_R64" => Intrinsic {
  53             inputs: { static INPUTS: [&'static Type; 1] = [&::U32]; &INPUTS },
  54             output: &::U32x16,
  55             definition: Named("llvm.hexagon.V6.lvsplatuw")
  56         },
  57         "V_vsplat_R128" => Intrinsic {
  58             inputs: { static INPUTS: [&'static Type; 1] = [&::U32]; &INPUTS },
  59             output: &::U32x32,
  60             definition: Named("llvm.hexagon.V6.lvsplatuw.128B")
  61         },
  62         "Q_and_QQ64" => Intrinsic {
  63             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  64             output: &::U32x2,
  65             definition: Named("llvm.hexagon.V6.pred.and")
  66         },
  67         "Q_and_QQ128" => Intrinsic {
  68             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  69             output: &::U32x4,
  70             definition: Named("llvm.hexagon.V6.pred.and.128B")
  71         },
  72         "Q_not_Q64" => Intrinsic {
  73             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
  74             output: &::U32x2,
  75             definition: Named("llvm.hexagon.V6.pred.not")
  76         },
  77         "Q_not_Q128" => Intrinsic {
  78             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
  79             output: &::U32x4,
  80             definition: Named("llvm.hexagon.V6.pred.not.128B")
  81         },
  82         "Q_or_QQ64" => Intrinsic {
  83             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  84             output: &::U32x2,
  85             definition: Named("llvm.hexagon.V6.pred.or")
  86         },
  87         "Q_or_QQ128" => Intrinsic {
  88             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  89             output: &::U32x4,
  90             definition: Named("llvm.hexagon.V6.pred.or.128B")
  91         },
  92         "Q_xor_QQ64" => Intrinsic {
  93             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  94             output: &::U32x2,
  95             definition: Named("llvm.hexagon.V6.pred.xor")
  96         },
  97         "Q_xor_QQ128" => Intrinsic {
  98             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  99             output: &::U32x4,
 100             definition: Named("llvm.hexagon.V6.pred.xor.128B")
 101         },
 102         "Vub_vabsdiff_VubVub64" => Intrinsic {
 103             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 104             output: &::U8x64,
 105             definition: Named("llvm.hexagon.V6.vabsdiffub")
 106         },
 107         "Vuh_vabsdiff_VuhVuh64" => Intrinsic {
 108             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
 109             output: &::U16x32,
 110             definition: Named("llvm.hexagon.V6.vabsdiffuh")
 111         },
 112         "Vub_vabsdiff_VubVub128" => Intrinsic {
 113             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 114             output: &::U8x128,
 115             definition: Named("llvm.hexagon.V6.vabsdiffub.128B")
 116         },
 117         "Vuh_vabsdiff_VuhVuh128" => Intrinsic {
 118             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 119             output: &::U16x64,
 120             definition: Named("llvm.hexagon.V6.vabsdiffuh.128B")
 121         },
 122         "Vuh_vabsdiff_VhVh64" => Intrinsic {
 123             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 124             output: &::U16x32,
 125             definition: Named("llvm.hexagon.V6.vabsdiffh")
 126         },
 127         "Vuw_vabsdiff_VwVw64" => Intrinsic {
 128             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 129             output: &::U32x16,
 130             definition: Named("llvm.hexagon.V6.vabsdiffw")
 131         },
 132         "Vuh_vabsdiff_VhVh128" => Intrinsic {
 133             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 134             output: &::U16x64,
 135             definition: Named("llvm.hexagon.V6.vabsdiffh.128B")
 136         },
 137         "Vuw_vabsdiff_VwVw128" => Intrinsic {
 138             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 139             output: &::U32x32,
 140             definition: Named("llvm.hexagon.V6.vabsdiffw.128B")
 141         },
 142         "Vh_vabs_Vh64" => Intrinsic {
 143             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
 144             output: &::I16x32,
 145             definition: Named("llvm.hexagon.V6.vabsh")
 146         },
 147         "Vw_vabs_Vw64" => Intrinsic {
 148             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS },
 149             output: &::I32x16,
 150             definition: Named("llvm.hexagon.V6.vabsw")
 151         },
 152         "Vh_vabs_Vh128" => Intrinsic {
 153             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
 154             output: &::I16x64,
 155             definition: Named("llvm.hexagon.V6.vabsh.128B")
 156         },
 157         "Vw_vabs_Vw128" => Intrinsic {
 158             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS },
 159             output: &::I32x32,
 160             definition: Named("llvm.hexagon.V6.vabsw.128B")
 161         },
 162         "Vh_vabs_Vh_sat64" => Intrinsic {
 163             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
 164             output: &::I16x32,
 165             definition: Named("llvm.hexagon.V6.vabsh.sat")
 166         },
 167         "Vw_vabs_Vw_sat64" => Intrinsic {
 168             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS },
 169             output: &::I32x16,
 170             definition: Named("llvm.hexagon.V6.vabsw.sat")
 171         },
 172         "Vh_vabs_Vh_sat128" => Intrinsic {
 173             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
 174             output: &::I16x64,
 175             definition: Named("llvm.hexagon.V6.vabsh.sat.128B")
 176         },
 177         "Vw_vabs_Vw_sat128" => Intrinsic {
 178             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS },
 179             output: &::I32x32,
 180             definition: Named("llvm.hexagon.V6.vabsw.sat.128B")
 181         },
 182         "Vb_vadd_VbVb64" => Intrinsic {
 183             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
 184             output: &::I8x64,
 185             definition: Named("llvm.hexagon.V6.vaddb")
 186         },
 187         "Vh_vadd_VhVh64" => Intrinsic {
 188             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 189             output: &::I16x32,
 190             definition: Named("llvm.hexagon.V6.vaddh")
 191         },
 192         "Vw_vadd_VwVw64" => Intrinsic {
 193             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 194             output: &::I32x16,
 195             definition: Named("llvm.hexagon.V6.vaddw")
 196         },
 197         "Vb_vadd_VbVb128" => Intrinsic {
 198             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
 199             output: &::I8x128,
 200             definition: Named("llvm.hexagon.V6.vaddb.128B")
 201         },
 202         "Vh_vadd_VhVh128" => Intrinsic {
 203             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 204             output: &::I16x64,
 205             definition: Named("llvm.hexagon.V6.vaddh.128B")
 206         },
 207         "Vw_vadd_VwVw128" => Intrinsic {
 208             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 209             output: &::I32x32,
 210             definition: Named("llvm.hexagon.V6.vaddw.128B")
 211         },
 212         "Vh_vadd_VhVh_sat64" => Intrinsic {
 213             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 214             output: &::I16x32,
 215             definition: Named("llvm.hexagon.V6.vaddhsat")
 216         },
 217         "Vw_vadd_VwVw_sat64" => Intrinsic {
 218             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 219             output: &::I32x16,
 220             definition: Named("llvm.hexagon.V6.vaddwsat")
 221         },
 222         "Vh_vadd_VhVh_sat128" => Intrinsic {
 223             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 224             output: &::I16x64,
 225             definition: Named("llvm.hexagon.V6.vaddhsat.128B")
 226         },
 227         "Vw_vadd_VwVw_sat128" => Intrinsic {
 228             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 229             output: &::I32x32,
 230             definition: Named("llvm.hexagon.V6.vaddwsat.128B")
 231         },
 232         "Vub_vadd_VubVub_sat64" => Intrinsic {
 233             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 234             output: &::U8x64,
 235             definition: Named("llvm.hexagon.V6.vaddubsat")
 236         },
 237         "Vuh_vadd_VuhVuh_sat64" => Intrinsic {
 238             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
 239             output: &::U16x32,
 240             definition: Named("llvm.hexagon.V6.vadduhsat")
 241         },
 242         "Vub_vadd_VubVub_sat128" => Intrinsic {
 243             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 244             output: &::U8x128,
 245             definition: Named("llvm.hexagon.V6.vaddubsat.128B")
 246         },
 247         "Vuh_vadd_VuhVuh_sat128" => Intrinsic {
 248             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 249             output: &::U16x64,
 250             definition: Named("llvm.hexagon.V6.vadduhsat.128B")
 251         },
 252         "Wb_vadd_WbWb64" => Intrinsic {
 253             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
 254             output: &::I8x128,
 255             definition: Named("llvm.hexagon.V6.vaddb.dv")
 256         },
 257         "Wh_vadd_WhWh64" => Intrinsic {
 258             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 259             output: &::I16x64,
 260             definition: Named("llvm.hexagon.V6.vaddh.dv")
 261         },
 262         "Ww_vadd_WwWw64" => Intrinsic {
 263             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 264             output: &::I32x32,
 265             definition: Named("llvm.hexagon.V6.vaddw.dv")
 266         },
 267         "Wb_vadd_WbWb128" => Intrinsic {
 268             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::I8x256]; &INPUTS },
 269             output: &::I8x256,
 270             definition: Named("llvm.hexagon.V6.vaddb.dv.128B")
 271         },
 272         "Wh_vadd_WhWh128" => Intrinsic {
 273             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS },
 274             output: &::I16x128,
 275             definition: Named("llvm.hexagon.V6.vaddh.dv.128B")
 276         },
 277         "Ww_vadd_WwWw128" => Intrinsic {
 278             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS },
 279             output: &::I32x64,
 280             definition: Named("llvm.hexagon.V6.vaddw.dv.128B")
 281         },
 282         "Wh_vadd_WhWh_sat64" => Intrinsic {
 283             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 284             output: &::I16x64,
 285             definition: Named("llvm.hexagon.V6.vaddhsat.dv")
 286         },
 287         "Ww_vadd_WwWw_sat64" => Intrinsic {
 288             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 289             output: &::I32x32,
 290             definition: Named("llvm.hexagon.V6.vaddwsat.dv")
 291         },
 292         "Wh_vadd_WhWh_sat128" => Intrinsic {
 293             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS },
 294             output: &::I16x128,
 295             definition: Named("llvm.hexagon.V6.vaddhsat.dv.128B")
 296         },
 297         "Ww_vadd_WwWw_sat128" => Intrinsic {
 298             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS },
 299             output: &::I32x64,
 300             definition: Named("llvm.hexagon.V6.vaddwsat.dv.128B")
 301         },
 302         "Wub_vadd_WubWub_sat64" => Intrinsic {
 303             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 304             output: &::U8x128,
 305             definition: Named("llvm.hexagon.V6.vaddubsat.dv")
 306         },
 307         "Wuh_vadd_WuhWuh_sat64" => Intrinsic {
 308             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 309             output: &::U16x64,
 310             definition: Named("llvm.hexagon.V6.vadduhsat.dv")
 311         },
 312         "Wub_vadd_WubWub_sat128" => Intrinsic {
 313             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS },
 314             output: &::U8x256,
 315             definition: Named("llvm.hexagon.V6.vaddubsat.dv.128B")
 316         },
 317         "Wuh_vadd_WuhWuh_sat128" => Intrinsic {
 318             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U16x128]; &INPUTS },
 319             output: &::U16x128,
 320             definition: Named("llvm.hexagon.V6.vadduhsat.dv.128B")
 321         },
 322         "V_valign_VVR64" => Intrinsic {
 323             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
 324             output: &::U8x64,
 325             definition: Named("llvm.hexagon.V6.valignb")
 326         },
 327         "V_valign_VVR128" => Intrinsic {
 328             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
 329             output: &::U8x128,
 330             definition: Named("llvm.hexagon.V6.valignb.128B")
 331         },
 332         "V_valign_VVI64" => Intrinsic {
 333             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
 334             output: &::U8x64,
 335             definition: Named("llvm.hexagon.V6.valignbi")
 336         },
 337         "V_valign_VVI128" => Intrinsic {
 338             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
 339             output: &::U8x128,
 340             definition: Named("llvm.hexagon.V6.valignbi.128B")
 341         },
 342         "V_vlalign_VVR64" => Intrinsic {
 343             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
 344             output: &::U8x64,
 345             definition: Named("llvm.hexagon.V6.vlalignb")
 346         },
 347         "V_vlalign_VVR128" => Intrinsic {
 348             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
 349             output: &::U8x128,
 350             definition: Named("llvm.hexagon.V6.vlalignb.128B")
 351         },
 352         "V_vlalign_VVI64" => Intrinsic {
 353             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
 354             output: &::U8x64,
 355             definition: Named("llvm.hexagon.V6.vlalignbi")
 356         },
 357         "V_vlalign_VVI128" => Intrinsic {
 358             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
 359             output: &::U8x128,
 360             definition: Named("llvm.hexagon.V6.vlalignbi.128B")
 361         },
 362         "V_vand_VV64" => Intrinsic {
 363             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
 364             output: &::U16x32,
 365             definition: Named("llvm.hexagon.V6.vand")
 366         },
 367         "V_vand_VV128" => Intrinsic {
 368             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 369             output: &::U16x64,
 370             definition: Named("llvm.hexagon.V6.vand.128B")
 371         },
 372         "V_vand_QR64" => Intrinsic {
 373             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32]; &INPUTS },
 374             output: &::U8x64,
 375             definition: Named("llvm.hexagon.V6.vandqrt")
 376         },
 377         "V_vand_QR128" => Intrinsic {
 378             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
 379             output: &::U8x128,
 380             definition: Named("llvm.hexagon.V6.vandqrt.128B")
 381         },
 382         "V_vandor_VQR64" => Intrinsic {
 383             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U32x2, &::U32]; &INPUTS },
 384             output: &::U8x64,
 385             definition: Named("llvm.hexagon.V6.vandqrt.acc")
 386         },
 387         "V_vandor_VQR128" => Intrinsic {
 388             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U32x4, &::U32]; &INPUTS },
 389             output: &::U8x128,
 390             definition: Named("llvm.hexagon.V6.vandqrt.acc.128B")
 391         },
 392         "Q_vand_VR64" => Intrinsic {
 393             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
 394             output: &::U32x2,
 395             definition: Named("llvm.hexagon.V6.vandvrt")
 396         },
 397         "Q_vand_VR128" => Intrinsic {
 398             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
 399             output: &::U32x4,
 400             definition: Named("llvm.hexagon.V6.vandvrt.128B")
 401         },
 402         "Q_vandor_QVR64" => Intrinsic {
 403             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U32]; &INPUTS },
 404             output: &::U32x2,
 405             definition: Named("llvm.hexagon.V6.vandvrt")
 406         },
 407         "Q_vandor_QVR128" => Intrinsic {
 408             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U32]; &INPUTS },
 409             output: &::U32x4,
 410             definition: Named("llvm.hexagon.V6.vandvrt.128B")
 411         },
 412         "Vh_vasl_VhR64" => Intrinsic {
 413             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
 414             output: &::I16x32,
 415             definition: Named("llvm.hexagon.V6.vaslh")
 416         },
 417         "Vw_vasl_VwR64" => Intrinsic {
 418             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS },
 419             output: &::I32x16,
 420             definition: Named("llvm.hexagon.V6.vaslw")
 421         },
 422         "Vh_vasl_VhR128" => Intrinsic {
 423             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 424             output: &::I16x64,
 425             definition: Named("llvm.hexagon.V6.vaslh.128B")
 426         },
 427         "Vw_vasl_VwR128" => Intrinsic {
 428             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
 429             output: &::I32x32,
 430             definition: Named("llvm.hexagon.V6.vaslw.128B")
 431         },
 432         "Vh_vasl_VhVh64" => Intrinsic {
 433             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 434             output: &::I16x32,
 435             definition: Named("llvm.hexagon.V6.vaslhv")
 436         },
 437         "Vw_vasl_VwVw64" => Intrinsic {
 438             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 439             output: &::I32x16,
 440             definition: Named("llvm.hexagon.V6.vaslwv")
 441         },
 442         "Vh_vasl_VhVh128" => Intrinsic {
 443             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 444             output: &::I16x64,
 445             definition: Named("llvm.hexagon.V6.vaslhv.128B")
 446         },
 447         "Vw_vasl_VwVw128" => Intrinsic {
 448             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 449             output: &::I32x32,
 450             definition: Named("llvm.hexagon.V6.vaslwv.128B")
 451         },
 452         "Vw_vaslacc_VwVwR64" => Intrinsic {
 453             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 454             output: &::I32x16,
 455             definition: Named("llvm.hexagon.V6.vaslw.acc")
 456         },
 457         "Vw_vaslacc_VwVwR128" => Intrinsic {
 458             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 459             output: &::I32x32,
 460             definition: Named("llvm.hexagon.V6.vaslw.acc.128B")
 461         },
 462         "Vh_vasr_VhR64" => Intrinsic {
 463             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
 464             output: &::I16x32,
 465             definition: Named("llvm.hexagon.V6.vasrh")
 466         },
 467         "Vw_vasr_VwR64" => Intrinsic {
 468             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS },
 469             output: &::I32x16,
 470             definition: Named("llvm.hexagon.V6.vasrw")
 471         },
 472         "Vh_vasr_VhR128" => Intrinsic {
 473             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 474             output: &::I16x64,
 475             definition: Named("llvm.hexagon.V6.vasrh.128B")
 476         },
 477         "Vw_vasr_VwR128" => Intrinsic {
 478             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
 479             output: &::I32x32,
 480             definition: Named("llvm.hexagon.V6.vasrw.128B")
 481         },
 482         "Vh_vasr_VhVh64" => Intrinsic {
 483             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 484             output: &::I16x32,
 485             definition: Named("llvm.hexagon.V6.vasrhv")
 486         },
 487         "Vw_vasr_VwVw64" => Intrinsic {
 488             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 489             output: &::I32x16,
 490             definition: Named("llvm.hexagon.V6.vasrwv")
 491         },
 492         "Vh_vasr_VhVh128" => Intrinsic {
 493             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 494             output: &::I16x64,
 495             definition: Named("llvm.hexagon.V6.vasrhv.128B")
 496         },
 497         "Vw_vasr_VwVw128" => Intrinsic {
 498             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 499             output: &::I32x32,
 500             definition: Named("llvm.hexagon.V6.vasrwv.128B")
 501         },
 502         "Vw_vasracc_VwVwR64" => Intrinsic {
 503             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 504             output: &::I32x16,
 505             definition: Named("llvm.hexagon.V6.vasrw.acc")
 506         },
 507         "Vw_vasracc_VwVwR128" => Intrinsic {
 508             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 509             output: &::I32x32,
 510             definition: Named("llvm.hexagon.V6.vasrw.acc.128B")
 511         },
 512         "Vh_vasr_VwVwR64" => Intrinsic {
 513             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 514             output: &::I16x32,
 515             definition: Named("llvm.hexagon.V6.vasrhw")
 516         },
 517         "Vh_vasr_VwVwR128" => Intrinsic {
 518             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 519             output: &::I16x64,
 520             definition: Named("llvm.hexagon.V6.vasrhw.128B")
 521         },
 522         "Vb_vasr_VhVhR_sat64" => Intrinsic {
 523             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS },
 524             output: &::I8x64,
 525             definition: Named("llvm.hexagon.V6.vasrhbsat")
 526         },
 527         "Vub_vasr_VhVhR_sat64" => Intrinsic {
 528             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS },
 529             output: &::U8x64,
 530             definition: Named("llvm.hexagon.V6.vasrhbsat")
 531         },
 532         "Vh_vasr_VwVwR_sat64" => Intrinsic {
 533             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 534             output: &::I16x32,
 535             definition: Named("llvm.hexagon.V6.vasrwhsat")
 536         },
 537         "Vuh_vasr_VwVwR_sat64" => Intrinsic {
 538             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 539             output: &::U16x32,
 540             definition: Named("llvm.hexagon.V6.vasrwhsat")
 541         },
 542         "Vb_vasr_VhVhR_sat128" => Intrinsic {
 543             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS },
 544             output: &::I8x128,
 545             definition: Named("llvm.hexagon.V6.vasrhbsat.128B")
 546         },
 547         "Vub_vasr_VhVhR_sat128" => Intrinsic {
 548             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS },
 549             output: &::U8x128,
 550             definition: Named("llvm.hexagon.V6.vasrhbsat.128B")
 551         },
 552         "Vh_vasr_VwVwR_sat128" => Intrinsic {
 553             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 554             output: &::I16x64,
 555             definition: Named("llvm.hexagon.V6.vasrwhsat.128B")
 556         },
 557         "Vuh_vasr_VwVwR_sat128" => Intrinsic {
 558             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 559             output: &::U16x64,
 560             definition: Named("llvm.hexagon.V6.vasrwhsat.128B")
 561         },
 562         "Vb_vasr_VhVhR_rnd_sat64" => Intrinsic {
 563             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS },
 564             output: &::I8x64,
 565             definition: Named("llvm.hexagon.V6.vasrhbrndsat")
 566         },
 567         "Vub_vasr_VhVhR_rnd_sat64" => Intrinsic {
 568             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS },
 569             output: &::U8x64,
 570             definition: Named("llvm.hexagon.V6.vasrhbrndsat")
 571         },
 572         "Vh_vasr_VwVwR_rnd_sat64" => Intrinsic {
 573             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 574             output: &::I16x32,
 575             definition: Named("llvm.hexagon.V6.vasrwhrndsat")
 576         },
 577         "Vuh_vasr_VwVwR_rnd_sat64" => Intrinsic {
 578             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
 579             output: &::U16x32,
 580             definition: Named("llvm.hexagon.V6.vasrwhrndsat")
 581         },
 582         "Vb_vasr_VhVhR_rnd_sat128" => Intrinsic {
 583             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS },
 584             output: &::I8x128,
 585             definition: Named("llvm.hexagon.V6.vasrhbrndsat.128B")
 586         },
 587         "Vub_vasr_VhVhR_rnd_sat128" => Intrinsic {
 588             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS },
 589             output: &::U8x128,
 590             definition: Named("llvm.hexagon.V6.vasrhbrndsat.128B")
 591         },
 592         "Vh_vasr_VwVwR_rnd_sat128" => Intrinsic {
 593             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 594             output: &::I16x64,
 595             definition: Named("llvm.hexagon.V6.vasrwhrndsat.128B")
 596         },
 597         "Vuh_vasr_VwVwR_rnd_sat128" => Intrinsic {
 598             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
 599             output: &::U16x64,
 600             definition: Named("llvm.hexagon.V6.vasrwhrndsat.128B")
 601         },
 602         "V_equals_V64" => Intrinsic {
 603             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x16]; &INPUTS },
 604             output: &::U32x16,
 605             definition: Named("llvm.hexagon.V6.vassign")
 606         },
 607         "V_equals_V128" => Intrinsic {
 608             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS },
 609             output: &::U32x32,
 610             definition: Named("llvm.hexagon.V6.vassign.128B")
 611         },
 612         "W_equals_W64" => Intrinsic {
 613             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS },
 614             output: &::U32x32,
 615             definition: Named("llvm.hexagon.V6.vassignp")
 616         },
 617         "W_equals_W128" => Intrinsic {
 618             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS },
 619             output: &::U32x64,
 620             definition: Named("llvm.hexagon.V6.vassignp.128B")
 621         },
 622         "Vh_vavg_VhVh64" => Intrinsic {
 623             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 624             output: &::I16x32,
 625             definition: Named("llvm.hexagon.V6.vavgh")
 626         },
 627         "Vw_vavg_VwVw64" => Intrinsic {
 628             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 629             output: &::I32x16,
 630             definition: Named("llvm.hexagon.V6.vavgw")
 631         },
 632         "Vh_vavg_VhVh128" => Intrinsic {
 633             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 634             output: &::I16x64,
 635             definition: Named("llvm.hexagon.V6.vavgh.128B")
 636         },
 637         "Vw_vavg_VwVw128" => Intrinsic {
 638             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 639             output: &::I32x32,
 640             definition: Named("llvm.hexagon.V6.vavgw.128B")
 641         },
 642         "Vub_vavg_VubVub64" => Intrinsic {
 643             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 644             output: &::U8x64,
 645             definition: Named("llvm.hexagon.V6.vavgub")
 646         },
 647         "Vuh_vavg_VuhVuh64" => Intrinsic {
 648             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
 649             output: &::U16x32,
 650             definition: Named("llvm.hexagon.V6.vavguh")
 651         },
 652         "Vub_vavg_VubVub128" => Intrinsic {
 653             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 654             output: &::U8x128,
 655             definition: Named("llvm.hexagon.V6.vavgub.128B")
 656         },
 657         "Vuh_vavg_VuhVuh128" => Intrinsic {
 658             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 659             output: &::U16x64,
 660             definition: Named("llvm.hexagon.V6.vavguh.128B")
 661         },
 662         "Vh_vavg_VhVh_rnd64" => Intrinsic {
 663             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 664             output: &::I16x32,
 665             definition: Named("llvm.hexagon.V6.vavgrndh")
 666         },
 667         "Vw_vavg_VwVw_rnd64" => Intrinsic {
 668             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
 669             output: &::I32x16,
 670             definition: Named("llvm.hexagon.V6.vavgrndw")
 671         },
 672         "Vh_vavg_VhVh_rnd128" => Intrinsic {
 673             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 674             output: &::I16x64,
 675             definition: Named("llvm.hexagon.V6.vavgrndh.128B")
 676         },
 677         "Vw_vavg_VwVw_rnd128" => Intrinsic {
 678             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
 679             output: &::I32x32,
 680             definition: Named("llvm.hexagon.V6.vavgrndw.128B")
 681         },
 682         "Vub_vavg_VubVub_rnd64" => Intrinsic {
 683             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 684             output: &::U8x64,
 685             definition: Named("llvm.hexagon.V6.vavgrndub")
 686         },
 687         "Vuh_vavg_VuhVuh_rnd64" => Intrinsic {
 688             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
 689             output: &::U16x32,
 690             definition: Named("llvm.hexagon.V6.vavgrnduh")
 691         },
 692         "Vub_vavg_VubVub_rnd128" => Intrinsic {
 693             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 694             output: &::U8x128,
 695             definition: Named("llvm.hexagon.V6.vavgrndub.128B")
 696         },
 697         "Vuh_vavg_VuhVuh_rnd128" => Intrinsic {
 698             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
 699             output: &::U16x64,
 700             definition: Named("llvm.hexagon.V6.vavgrnduh.128B")
 701         },
 702         "Vuh_vcl0_Vuh64" => Intrinsic {
 703             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS },
 704             output: &::U16x32,
 705             definition: Named("llvm.hexagon.V6.vcl0h")
 706         },
 707         "Vuw_vcl0_Vuw64" => Intrinsic {
 708             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x16]; &INPUTS },
 709             output: &::U32x16,
 710             definition: Named("llvm.hexagon.V6.vcl0w")
 711         },
 712         "Vuh_vcl0_Vuh128" => Intrinsic {
 713             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS },
 714             output: &::U16x64,
 715             definition: Named("llvm.hexagon.V6.vcl0h.128B")
 716         },
 717         "Vuw_vcl0_Vuw128" => Intrinsic {
 718             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS },
 719             output: &::U32x32,
 720             definition: Named("llvm.hexagon.V6.vcl0w.128B")
 721         },
 722         "W_vcombine_VV64" => Intrinsic {
 723             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 724             output: &::U8x128,
 725             definition: Named("llvm.hexagon.V6.vcombine")
 726         },
 727         "W_vcombine_VV128" => Intrinsic {
 728             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 729             output: &::U8x256,
 730             definition: Named("llvm.hexagon.V6.vcombine.128B")
 731         },
 732         "V_vzero64" => Intrinsic {
 733             inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
 734             output: &::U32x16,
 735             definition: Named("llvm.hexagon.V6.vd0")
 736         },
 737         "V_vzero128" => Intrinsic {
 738             inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
 739             output: &::U32x32,
 740             definition: Named("llvm.hexagon.V6.vd0.128B")
 741         },
 742         "Vb_vdeal_Vb64" => Intrinsic {
 743             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS },
 744             output: &::I8x64,
 745             definition: Named("llvm.hexagon.V6.vdealb")
 746         },
 747         "Vh_vdeal_Vh64" => Intrinsic {
 748             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
 749             output: &::I16x32,
 750             definition: Named("llvm.hexagon.V6.vdealh")
 751         },
 752         "Vb_vdeal_Vb128" => Intrinsic {
 753             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS },
 754             output: &::I8x128,
 755             definition: Named("llvm.hexagon.V6.vdealb.128B")
 756         },
 757         "Vh_vdeal_Vh128" => Intrinsic {
 758             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
 759             output: &::I16x64,
 760             definition: Named("llvm.hexagon.V6.vdealh.128B")
 761         },
 762         "Vb_vdeale_VbVb64" => Intrinsic {
 763             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
 764             output: &::I8x64,
 765             definition: Named("llvm.hexagon.V6.vdealb4w")
 766         },
 767         "Vb_vdeale_VbVb128" => Intrinsic {
 768             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
 769             output: &::I8x128,
 770             definition: Named("llvm.hexagon.V6.vdealb4w.128B")
 771         },
 772         "W_vdeal_VVR64" => Intrinsic {
 773             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
 774             output: &::U8x128,
 775             definition: Named("llvm.hexagon.V6.vdealvdd")
 776         },
 777         "W_vdeal_VVR128" => Intrinsic {
 778             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
 779             output: &::U8x256,
 780             definition: Named("llvm.hexagon.V6.vdealvdd.128B")
 781         },
 782         "V_vdelta_VV64" => Intrinsic {
 783             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
 784             output: &::U8x64,
 785             definition: Named("llvm.hexagon.V6.vdelta")
 786         },
 787         "V_vdelta_VV128" => Intrinsic {
 788             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
 789             output: &::U8x128,
 790             definition: Named("llvm.hexagon.V6.vdelta.128B")
 791         },
 792         "Vh_vdmpy_VubRb64" => Intrinsic {
 793             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
 794             output: &::I16x32,
 795             definition: Named("llvm.hexagon.V6.vdmpybus")
 796         },
 797         "Vh_vdmpy_VubRb128" => Intrinsic {
 798             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
 799             output: &::I16x64,
 800             definition: Named("llvm.hexagon.V6.vdmpybus.128B")
 801         },
 802         "Vh_vdmpyacc_VhVubRb64" => Intrinsic {
 803             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::U8x64, &::U32]; &INPUTS },
 804             output: &::I16x32,
 805             definition: Named("llvm.hexagon.V6.vdmpybus.acc")
 806         },
 807         "Vh_vdmpyacc_VhVubRb128" => Intrinsic {
 808             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS },
 809             output: &::I16x64,
 810             definition: Named("llvm.hexagon.V6.vdmpybus.acc.128B")
 811         },
 812         "Wh_vdmpy_WubRb64" => Intrinsic {
 813             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
 814             output: &::I16x64,
 815             definition: Named("llvm.hexagon.V6.vdmpybus.dv")
 816         },
 817         "Wh_vdmpy_WubRb128" => Intrinsic {
 818             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
 819             output: &::I16x128,
 820             definition: Named("llvm.hexagon.V6.vdmpybus.dv.128B")
 821         },
 822         "Wh_vdmpyacc_WhWubRb64" => Intrinsic {
 823             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS },
 824             output: &::I16x64,
 825             definition: Named("llvm.hexagon.V6.vdmpybus.dv.acc")
 826         },
 827         "Wh_vdmpyacc_WhWubRb128" => Intrinsic {
 828             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS },
 829             output: &::I16x128,
 830             definition: Named("llvm.hexagon.V6.vdmpybus.dv.acc.128B")
 831         },
 832         "Vw_vdmpy_VhRb64" => Intrinsic {
 833             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
 834             output: &::I32x16,
 835             definition: Named("llvm.hexagon.V6.vdmpyhb")
 836         },
 837         "Vw_vdmpy_VhRb128" => Intrinsic {
 838             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 839             output: &::I32x32,
 840             definition: Named("llvm.hexagon.V6.vdmpyhb.128B")
 841         },
 842         "Vw_vdmpyacc_VwVhRb64" => Intrinsic {
 843             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS },
 844             output: &::I32x16,
 845             definition: Named("llvm.hexagon.V6.vdmpyhb.acc")
 846         },
 847         "Vw_vdmpyacc_VwVhRb128" => Intrinsic {
 848             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
 849             output: &::I32x32,
 850             definition: Named("llvm.hexagon.V6.vdmpyhb.acc.128B")
 851         },
 852         "Ww_vdmpy_WhRb64" => Intrinsic {
 853             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 854             output: &::I32x32,
 855             definition: Named("llvm.hexagon.V6.vdmpyhb.dv")
 856         },
 857         "Ww_vdmpy_WhRb128" => Intrinsic {
 858             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS },
 859             output: &::I32x64,
 860             definition: Named("llvm.hexagon.V6.vdmpyhb.dv.128B")
 861         },
 862         "Ww_vdmpyacc_WwWhRb64" => Intrinsic {
 863             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
 864             output: &::I32x32,
 865             definition: Named("llvm.hexagon.V6.vdmpyhb.dv.acc")
 866         },
 867         "Ww_vdmpyacc_WwWhRb128" => Intrinsic {
 868             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS },
 869             output: &::I32x64,
 870             definition: Named("llvm.hexagon.V6.vdmpyhb.dv.acc.128B")
 871         },
 872         "Vw_vdmpy_WwRh_sat64" => Intrinsic {
 873             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
 874             output: &::I32x16,
 875             definition: Named("llvm.hexagon.V6.vdmpyhisat")
 876         },
 877         "Vw_vdmpy_WwRh_sat128" => Intrinsic {
 878             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::U32]; &INPUTS },
 879             output: &::I32x32,
 880             definition: Named("llvm.hexagon.V6.vdmpyhisat.128B")
 881         },
 882         "Vw_vdmpy_VhRh_sat64" => Intrinsic {
 883             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
 884             output: &::I32x16,
 885             definition: Named("llvm.hexagon.V6.vdmpyhsat")
 886         },
 887         "Vw_vdmpy_VhRh_sat128" => Intrinsic {
 888             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 889             output: &::I32x32,
 890             definition: Named("llvm.hexagon.V6.vdmpyhsat.128B")
 891         },
 892         "Vw_vdmpy_WhRuh_sat64" => Intrinsic {
 893             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 894             output: &::I32x16,
 895             definition: Named("llvm.hexagon.V6.vdmpyhsuisat")
 896         },
 897         "Vw_vdmpy_WhRuh_sat128" => Intrinsic {
 898             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS },
 899             output: &::I32x32,
 900             definition: Named("llvm.hexagon.V6.vdmpyhsuisat.128B")
 901         },
 902         "Vw_vdmpy_VhRuh_sat64" => Intrinsic {
 903             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
 904             output: &::I32x16,
 905             definition: Named("llvm.hexagon.V6.vdmpyhsusat")
 906         },
 907         "Vw_vdmpy_VhRuh_sat128" => Intrinsic {
 908             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
 909             output: &::I32x32,
 910             definition: Named("llvm.hexagon.V6.vdmpyhsusat.128B")
 911         },
 912         "Vw_vdmpy_VhVh_sat64" => Intrinsic {
 913             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 914             output: &::I32x16,
 915             definition: Named("llvm.hexagon.V6.vdmpyhvsat")
 916         },
 917         "Vw_vdmpy_VhVh_sat128" => Intrinsic {
 918             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
 919             output: &::I32x32,
 920             definition: Named("llvm.hexagon.V6.vdmpyhvsat.128B")
 921         },
 922         "Vw_vdmpyacc_VwWwRh_sat64" => Intrinsic {
 923             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x32, &::U32]; &INPUTS },
 924             output: &::I32x16,
 925             definition: Named("llvm.hexagon.V6.vdmpyhisat_acc")
 926         },
 927         "Vw_vdmpyacc_VwWwRh_sat128" => Intrinsic {
 928             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x64, &::U32]; &INPUTS },
 929             output: &::I32x32,
 930             definition: Named("llvm.hexagon.V6.vdmpyhisat_acc.128B")
 931         },
 932         "Wuw_vdsad_WuhRuh64" => Intrinsic {
 933             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS },
 934             output: &::U32x32,
 935             definition: Named("llvm.hexagon.V6.vdsaduh")
 936         },
 937         "Wuw_vdsad_WuhRuh128" => Intrinsic {
 938             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U32]; &INPUTS },
 939             output: &::U32x64,
 940             definition: Named("llvm.hexagon.V6.vdsaduh.128B")
 941         },
 942         "Wuw_vdsadacc_WuwWuhRuh64" => Intrinsic {
 943             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x64, &::U32]; &INPUTS },
 944             output: &::U32x32,
 945             definition: Named("llvm.hexagon.V6.vdsaduh.acc")
 946         },
 947         "Wuw_vdsadacc_WuwWuhRuh128" => Intrinsic {
 948             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x128, &::U32]; &INPUTS },
 949             output: &::U32x64,
 950             definition: Named("llvm.hexagon.V6.vdsaduh.acc.128B")
 951         },
 952         "Vw_vdmpyacc_VwVhRh_sat64" => Intrinsic {
 953             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS },
 954             output: &::I32x16,
 955             definition: Named("llvm.hexagon.V6.vdmpyhsat_acc")
 956         },
 957         "Vw_vdmpyacc_VwVhRh_sat128" => Intrinsic {
 958             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
 959             output: &::I32x32,
 960             definition: Named("llvm.hexagon.V6.vdmpyhsat_acc.128B")
 961         },
 962         "Vw_vdmpyacc_VwWhRuh_sat64" => Intrinsic {
 963             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x64, &::U32]; &INPUTS },
 964             output: &::I32x16,
 965             definition: Named("llvm.hexagon.V6.vdmpyhsuisat_acc")
 966         },
 967         "Vw_vdmpyacc_VwWhRuh_sat128" => Intrinsic {
 968             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x128, &::U32]; &INPUTS },
 969             output: &::I32x32,
 970             definition: Named("llvm.hexagon.V6.vdmpyhsuisat_acc.128B")
 971         },
 972         "Vw_vdmpyacc_VwVhRuh_sat64" => Intrinsic {
 973             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS },
 974             output: &::I32x16,
 975             definition: Named("llvm.hexagon.V6.vdmpyhsusat_acc")
 976         },
 977         "Vw_vdmpyacc_VwVhRuh_sat128" => Intrinsic {
 978             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
 979             output: &::I32x32,
 980             definition: Named("llvm.hexagon.V6.vdmpyhsusat_acc.128B")
 981         },
 982         "Vw_vdmpyacc_VwVhVh_sat64" => Intrinsic {
 983             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::I16x32]; &INPUTS },
 984             output: &::I32x16,
 985             definition: Named("llvm.hexagon.V6.vdmpyhvsat_acc")
 986         },
 987         "Vw_vdmpyacc_VwVhVh_sat128" => Intrinsic {
 988             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::I16x64]; &INPUTS },
 989             output: &::I32x32,
 990             definition: Named("llvm.hexagon.V6.vdmpyhvsat_acc.128B")
 991         },
 992         "Q_vcmp_eq_VbVb64" => Intrinsic {
 993             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
 994             output: &::U32x2,
 995             definition: Named("llvm.hexagon.V6.veqb")
 996         },
 997         "Q_vcmp_eq_VhVh64" => Intrinsic {
 998             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
 999             output: &::U32x2,
1000             definition: Named("llvm.hexagon.V6.veqh")
1001         },
1002         "Q_vcmp_eq_VwVw64" => Intrinsic {
1003             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1004             output: &::U32x2,
1005             definition: Named("llvm.hexagon.V6.veqw")
1006         },
1007         "Q_vcmp_eq_VbVb128" => Intrinsic {
1008             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
1009             output: &::U32x4,
1010             definition: Named("llvm.hexagon.V6.veqb.128B")
1011         },
1012         "Q_vcmp_eq_VhVh128" => Intrinsic {
1013             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1014             output: &::U32x4,
1015             definition: Named("llvm.hexagon.V6.veqh.128B")
1016         },
1017         "Q_vcmp_eq_VwVw128" => Intrinsic {
1018             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
1019             output: &::U32x4,
1020             definition: Named("llvm.hexagon.V6.veqw.128B")
1021         },
1022         "Q_vcmp_eqand_QVbVb64" => Intrinsic {
1023             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1024             output: &::U32x2,
1025             definition: Named("llvm.hexagon.V6.veqb.and")
1026         },
1027         "Q_vcmp_eqand_QVhVh64" => Intrinsic {
1028             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1029             output: &::U32x2,
1030             definition: Named("llvm.hexagon.V6.veqh.and")
1031         },
1032         "Q_vcmp_eqand_QVwVw64" => Intrinsic {
1033             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1034             output: &::U32x2,
1035             definition: Named("llvm.hexagon.V6.veqw.and")
1036         },
1037         "Q_vcmp_eqand_QVbVb128" => Intrinsic {
1038             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1039             output: &::U32x4,
1040             definition: Named("llvm.hexagon.V6.veqb.and.128B")
1041         },
1042         "Q_vcmp_eqand_QVhVh128" => Intrinsic {
1043             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1044             output: &::U32x4,
1045             definition: Named("llvm.hexagon.V6.veqh.and.128B")
1046         },
1047         "Q_vcmp_eqand_QVwVw128" => Intrinsic {
1048             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1049             output: &::U32x4,
1050             definition: Named("llvm.hexagon.V6.veqw.and.128B")
1051         },
1052         "Q_vcmp_eqor_QVbVb64" => Intrinsic {
1053             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1054             output: &::U32x2,
1055             definition: Named("llvm.hexagon.V6.veqb.or")
1056         },
1057         "Q_vcmp_eqor_QVhVh64" => Intrinsic {
1058             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1059             output: &::U32x2,
1060             definition: Named("llvm.hexagon.V6.veqh.or")
1061         },
1062         "Q_vcmp_eqor_QVwVw64" => Intrinsic {
1063             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1064             output: &::U32x2,
1065             definition: Named("llvm.hexagon.V6.veqw.or")
1066         },
1067         "Q_vcmp_eqor_QVbVb128" => Intrinsic {
1068             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1069             output: &::U32x4,
1070             definition: Named("llvm.hexagon.V6.veqb.or.128B")
1071         },
1072         "Q_vcmp_eqor_QVhVh128" => Intrinsic {
1073             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1074             output: &::U32x4,
1075             definition: Named("llvm.hexagon.V6.veqh.or.128B")
1076         },
1077         "Q_vcmp_eqor_QVwVw128" => Intrinsic {
1078             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1079             output: &::U32x4,
1080             definition: Named("llvm.hexagon.V6.veqw.or.128B")
1081         },
1082         "Q_vcmp_eqxacc_QVbVb64" => Intrinsic {
1083             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1084             output: &::U32x2,
1085             definition: Named("llvm.hexagon.V6.veqb.xor")
1086         },
1087         "Q_vcmp_eqxacc_QVhVh64" => Intrinsic {
1088             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1089             output: &::U32x2,
1090             definition: Named("llvm.hexagon.V6.veqh.xor")
1091         },
1092         "Q_vcmp_eqxacc_QVwVw64" => Intrinsic {
1093             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1094             output: &::U32x2,
1095             definition: Named("llvm.hexagon.V6.veqw.xor")
1096         },
1097         "Q_vcmp_eqxacc_QVbVb128" => Intrinsic {
1098             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1099             output: &::U32x4,
1100             definition: Named("llvm.hexagon.V6.veqb.xor.128B")
1101         },
1102         "Q_vcmp_eqxacc_QVhVh128" => Intrinsic {
1103             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1104             output: &::U32x4,
1105             definition: Named("llvm.hexagon.V6.veqh.xor.128B")
1106         },
1107         "Q_vcmp_eqxacc_QVwVw128" => Intrinsic {
1108             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1109             output: &::U32x4,
1110             definition: Named("llvm.hexagon.V6.veqw.xor.128B")
1111         },
1112         "Q_vcmp_gt_VbVb64" => Intrinsic {
1113             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
1114             output: &::U32x2,
1115             definition: Named("llvm.hexagon.V6.vgtb")
1116         },
1117         "Q_vcmp_gt_VhVh64" => Intrinsic {
1118             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1119             output: &::U32x2,
1120             definition: Named("llvm.hexagon.V6.vgth")
1121         },
1122         "Q_vcmp_gt_VwVw64" => Intrinsic {
1123             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1124             output: &::U32x2,
1125             definition: Named("llvm.hexagon.V6.vgtw")
1126         },
1127         "Q_vcmp_gt_VbVb128" => Intrinsic {
1128             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
1129             output: &::U32x4,
1130             definition: Named("llvm.hexagon.V6.vgtb.128B")
1131         },
1132         "Q_vcmp_gt_VhVh128" => Intrinsic {
1133             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1134             output: &::U32x4,
1135             definition: Named("llvm.hexagon.V6.vgth.128B")
1136         },
1137         "Q_vcmp_gt_VwVw128" => Intrinsic {
1138             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
1139             output: &::U32x4,
1140             definition: Named("llvm.hexagon.V6.vgtw.128B")
1141         },
1142         "Q_vcmp_gt_VubVub64" => Intrinsic {
1143             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
1144             output: &::U32x2,
1145             definition: Named("llvm.hexagon.V6.vgtub")
1146         },
1147         "Q_vcmp_gt_VuhVuh64" => Intrinsic {
1148             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
1149             output: &::U32x2,
1150             definition: Named("llvm.hexagon.V6.vgtuh")
1151         },
1152         "Q_vcmp_gt_VubVub128" => Intrinsic {
1153             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
1154             output: &::U32x4,
1155             definition: Named("llvm.hexagon.V6.vgtub.128B")
1156         },
1157         "Q_vcmp_gt_VuhVuh128" => Intrinsic {
1158             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
1159             output: &::U32x4,
1160             definition: Named("llvm.hexagon.V6.vgtuh.128B")
1161         },
1162         "Q_vcmp_gtand_QVbVb64" => Intrinsic {
1163             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1164             output: &::U32x2,
1165             definition: Named("llvm.hexagon.V6.vgtb.and")
1166         },
1167         "Q_vcmp_gtand_QVhVh64" => Intrinsic {
1168             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1169             output: &::U32x2,
1170             definition: Named("llvm.hexagon.V6.vgth.and")
1171         },
1172         "Q_vcmp_gtand_QVwVw64" => Intrinsic {
1173             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1174             output: &::U32x2,
1175             definition: Named("llvm.hexagon.V6.vgtw.and")
1176         },
1177         "Q_vcmp_gtand_QVbVb128" => Intrinsic {
1178             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1179             output: &::U32x4,
1180             definition: Named("llvm.hexagon.V6.vgtb.and.128B")
1181         },
1182         "Q_vcmp_gtand_QVhVh128" => Intrinsic {
1183             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1184             output: &::U32x4,
1185             definition: Named("llvm.hexagon.V6.vgth.and.128B")
1186         },
1187         "Q_vcmp_gtand_QVwVw128" => Intrinsic {
1188             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1189             output: &::U32x4,
1190             definition: Named("llvm.hexagon.V6.vgtw.and.128B")
1191         },
1192         "Q_vcmp_gtand_QVubVub64" => Intrinsic {
1193             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS },
1194             output: &::U32x2,
1195             definition: Named("llvm.hexagon.V6.vgtub.and")
1196         },
1197         "Q_vcmp_gtand_QVuhVuh64" => Intrinsic {
1198             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS },
1199             output: &::U32x2,
1200             definition: Named("llvm.hexagon.V6.vgtuh.and")
1201         },
1202         "Q_vcmp_gtand_QVubVub128" => Intrinsic {
1203             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS },
1204             output: &::U32x4,
1205             definition: Named("llvm.hexagon.V6.vgtub.and.128B")
1206         },
1207         "Q_vcmp_gtand_QVuhVuh128" => Intrinsic {
1208             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS },
1209             output: &::U32x4,
1210             definition: Named("llvm.hexagon.V6.vgtuh.and.128B")
1211         },
1212         "Q_vcmp_gtor_QVbVb64" => Intrinsic {
1213             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1214             output: &::U32x2,
1215             definition: Named("llvm.hexagon.V6.vgtb.or")
1216         },
1217         "Q_vcmp_gtor_QVhVh64" => Intrinsic {
1218             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1219             output: &::U32x2,
1220             definition: Named("llvm.hexagon.V6.vgth.or")
1221         },
1222         "Q_vcmp_gtor_QVwVw64" => Intrinsic {
1223             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1224             output: &::U32x2,
1225             definition: Named("llvm.hexagon.V6.vgtw.or")
1226         },
1227         "Q_vcmp_gtor_QVbVb128" => Intrinsic {
1228             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1229             output: &::U32x4,
1230             definition: Named("llvm.hexagon.V6.vgtb.or.128B")
1231         },
1232         "Q_vcmp_gtor_QVhVh128" => Intrinsic {
1233             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1234             output: &::U32x4,
1235             definition: Named("llvm.hexagon.V6.vgth.or.128B")
1236         },
1237         "Q_vcmp_gtor_QVwVw128" => Intrinsic {
1238             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1239             output: &::U32x4,
1240             definition: Named("llvm.hexagon.V6.vgtw.or.128B")
1241         },
1242         "Q_vcmp_gtor_QVubVub64" => Intrinsic {
1243             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS },
1244             output: &::U32x2,
1245             definition: Named("llvm.hexagon.V6.vgtub.or")
1246         },
1247         "Q_vcmp_gtor_QVuhVuh64" => Intrinsic {
1248             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS },
1249             output: &::U32x2,
1250             definition: Named("llvm.hexagon.V6.vgtuh.or")
1251         },
1252         "Q_vcmp_gtor_QVubVub128" => Intrinsic {
1253             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS },
1254             output: &::U32x4,
1255             definition: Named("llvm.hexagon.V6.vgtub.or.128B")
1256         },
1257         "Q_vcmp_gtor_QVuhVuh128" => Intrinsic {
1258             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS },
1259             output: &::U32x4,
1260             definition: Named("llvm.hexagon.V6.vgtuh.or.128B")
1261         },
1262         "Q_vcmp_gtxacc_QVbVb64" => Intrinsic {
1263             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
1264             output: &::U32x2,
1265             definition: Named("llvm.hexagon.V6.vgtb.xor")
1266         },
1267         "Q_vcmp_gtxacc_QVhVh64" => Intrinsic {
1268             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
1269             output: &::U32x2,
1270             definition: Named("llvm.hexagon.V6.vgth.xor")
1271         },
1272         "Q_vcmp_gtxacc_QVwVw64" => Intrinsic {
1273             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
1274             output: &::U32x2,
1275             definition: Named("llvm.hexagon.V6.vgtw.xor")
1276         },
1277         "Q_vcmp_gtxacc_QVbVb128" => Intrinsic {
1278             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
1279             output: &::U32x4,
1280             definition: Named("llvm.hexagon.V6.vgtb.xor.128B")
1281         },
1282         "Q_vcmp_gtxacc_QVhVh128" => Intrinsic {
1283             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
1284             output: &::U32x4,
1285             definition: Named("llvm.hexagon.V6.vgth.xor.128B")
1286         },
1287         "Q_vcmp_gtxacc_QVwVw128" => Intrinsic {
1288             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
1289             output: &::U32x4,
1290             definition: Named("llvm.hexagon.V6.vgtw.xor.128B")
1291         },
1292         "Q_vcmp_gtxacc_QVubVub64" => Intrinsic {
1293             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS },
1294             output: &::U32x2,
1295             definition: Named("llvm.hexagon.V6.vgtub.xor")
1296         },
1297         "Q_vcmp_gtxacc_QVuhVuh64" => Intrinsic {
1298             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS },
1299             output: &::U32x2,
1300             definition: Named("llvm.hexagon.V6.vgtuh.xor")
1301         },
1302         "Q_vcmp_gtxacc_QVubVub128" => Intrinsic {
1303             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS },
1304             output: &::U32x4,
1305             definition: Named("llvm.hexagon.V6.vgtub.xor.128B")
1306         },
1307         "Q_vcmp_gtxacc_QVuhVuh128" => Intrinsic {
1308             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS },
1309             output: &::U32x4,
1310             definition: Named("llvm.hexagon.V6.vgtuh.xor.128B")
1311         },
1312         "Vw_vinsert_VwR64" => Intrinsic {
1313             inputs: { static INPUTS: [&'static Type; 1] = [&::I32]; &INPUTS },
1314             output: &::I32x16,
1315             definition: Named("llvm.hexagon.V6.vinsertwr")
1316         },
1317         "Vw_vinsert_VwR128" => Intrinsic {
1318             inputs: { static INPUTS: [&'static Type; 1] = [&::I32]; &INPUTS },
1319             output: &::I32x32,
1320             definition: Named("llvm.hexagon.V6.vinsertwr.128B")
1321         },
1322         "Vuh_vlsr_VuhR64" => Intrinsic {
1323             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U32]; &INPUTS },
1324             output: &::U16x32,
1325             definition: Named("llvm.hexagon.V6.vlsrh")
1326         },
1327         "Vuw_vlsr_VuwR64" => Intrinsic {
1328             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32]; &INPUTS },
1329             output: &::U32x16,
1330             definition: Named("llvm.hexagon.V6.vlsrw")
1331         },
1332         "Vuh_vlsr_VuhR128" => Intrinsic {
1333             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS },
1334             output: &::U16x64,
1335             definition: Named("llvm.hexagon.V6.vlsrh.128B")
1336         },
1337         "Vuw_vlsr_VuwR128" => Intrinsic {
1338             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32]; &INPUTS },
1339             output: &::U32x32,
1340             definition: Named("llvm.hexagon.V6.vlsrw.128B")
1341         },
1342         "Vh_vlsr_VhVh64" => Intrinsic {
1343             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1344             output: &::I16x32,
1345             definition: Named("llvm.hexagon.V6.vlsrhv")
1346         },
1347         "Vw_vlsr_VwVw64" => Intrinsic {
1348             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1349             output: &::I32x16,
1350             definition: Named("llvm.hexagon.V6.vlsrwv")
1351         },
1352         "Vh_vlsr_VhVh128" => Intrinsic {
1353             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1354             output: &::I16x64,
1355             definition: Named("llvm.hexagon.V6.vlsrhv.128B")
1356         },
1357         "Vw_vlsr_VwVw128" => Intrinsic {
1358             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
1359             output: &::I32x32,
1360             definition: Named("llvm.hexagon.V6.vlsrwv.128B")
1361         },
1362         "Vb_vlut32_VbVbR64" => Intrinsic {
1363             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x64, &::I8x64, &::U32]; &INPUTS },
1364             output: &::I8x64,
1365             definition: Named("llvm.hexagon.V6.vlutvvb")
1366         },
1367         "Vb_vlut32_VbVbR128" => Intrinsic {
1368             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x128, &::I8x128, &::U32]; &INPUTS },
1369             output: &::I8x128,
1370             definition: Named("llvm.hexagon.V6.vlutvvb.128B")
1371         },
1372         "Wh_vlut16_VbVhR64" => Intrinsic {
1373             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x64, &::I16x32, &::U32]; &INPUTS },
1374             output: &::I16x64,
1375             definition: Named("llvm.hexagon.V6.vlutvwh")
1376         },
1377         "Wh_vlut16_VbVhR128" => Intrinsic {
1378             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x128, &::I16x64, &::U32]; &INPUTS },
1379             output: &::I16x128,
1380             definition: Named("llvm.hexagon.V6.vlutvwh.128B")
1381         },
1382         "Vb_vlut32or_VbVbVbR64" => Intrinsic {
1383             inputs: { static INPUTS: [&'static Type; 4] = [&::I8x64, &::I8x64, &::I8x64, &::U32]; &INPUTS },
1384             output: &::I8x64,
1385             definition: Named("llvm.hexagon.V6.vlutvvb.oracc")
1386         },
1387         "Vb_vlut32or_VbVbVbR128" => Intrinsic {
1388             inputs: { static INPUTS: [&'static Type; 4] = [&::I8x128, &::I8x128, &::I8x128, &::U32]; &INPUTS },
1389             output: &::I8x128,
1390             definition: Named("llvm.hexagon.V6.vlutvvb.oracc.128B")
1391         },
1392         "Wh_vlut16or_WhVbVhR64" => Intrinsic {
1393             inputs: { static INPUTS: [&'static Type; 4] = [&::I16x64, &::I8x64, &::I16x32, &::U32]; &INPUTS },
1394             output: &::I16x64,
1395             definition: Named("llvm.hexagon.V6.vlutvwh.oracc")
1396         },
1397         "Wh_vlut16or_WhVbVhR128" => Intrinsic {
1398             inputs: { static INPUTS: [&'static Type; 4] = [&::I16x128, &::I8x128, &::I16x64, &::U32]; &INPUTS },
1399             output: &::I16x128,
1400             definition: Named("llvm.hexagon.V6.vlutvwh.oracc.128B")
1401         },
1402         "Vh_vmax_VhVh64" => Intrinsic {
1403             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1404             output: &::I16x32,
1405             definition: Named("llvm.hexagon.V6.vmaxh")
1406         },
1407         "Vw_vmax_VwVw64" => Intrinsic {
1408             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1409             output: &::I32x16,
1410             definition: Named("llvm.hexagon.V6.vmaxw")
1411         },
1412         "Vh_vmax_VhVh128" => Intrinsic {
1413             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1414             output: &::I16x64,
1415             definition: Named("llvm.hexagon.V6.vmaxh.128B")
1416         },
1417         "Vw_vmax_VwVw128" => Intrinsic {
1418             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
1419             output: &::I32x32,
1420             definition: Named("llvm.hexagon.V6.vmaxw.128B")
1421         },
1422         "Vub_vmax_VubVub64" => Intrinsic {
1423             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
1424             output: &::U8x64,
1425             definition: Named("llvm.hexagon.V6.vmaxub")
1426         },
1427         "Vuh_vmax_VuhVuh64" => Intrinsic {
1428             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
1429             output: &::U16x32,
1430             definition: Named("llvm.hexagon.V6.vmaxuh")
1431         },
1432         "Vub_vmax_VubVub128" => Intrinsic {
1433             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
1434             output: &::U8x128,
1435             definition: Named("llvm.hexagon.V6.vmaxub.128B")
1436         },
1437         "Vuh_vmax_VuhVuh128" => Intrinsic {
1438             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
1439             output: &::U16x64,
1440             definition: Named("llvm.hexagon.V6.vmaxuh.128B")
1441         },
1442         "Vh_vmin_VhVh64" => Intrinsic {
1443             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1444             output: &::I16x32,
1445             definition: Named("llvm.hexagon.V6.vminh")
1446         },
1447         "Vw_vmin_VwVw64" => Intrinsic {
1448             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1449             output: &::I32x16,
1450             definition: Named("llvm.hexagon.V6.vminw")
1451         },
1452         "Vh_vmin_VhVh128" => Intrinsic {
1453             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1454             output: &::I16x64,
1455             definition: Named("llvm.hexagon.V6.vminh.128B")
1456         },
1457         "Vw_vmin_VwVw128" => Intrinsic {
1458             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
1459             output: &::I32x32,
1460             definition: Named("llvm.hexagon.V6.vminw.128B")
1461         },
1462         "Vub_vmin_VubVub64" => Intrinsic {
1463             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
1464             output: &::U8x64,
1465             definition: Named("llvm.hexagon.V6.vminub")
1466         },
1467         "Vuh_vmin_VuhVuh64" => Intrinsic {
1468             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
1469             output: &::U16x32,
1470             definition: Named("llvm.hexagon.V6.vminuh")
1471         },
1472         "Vub_vmin_VubVub128" => Intrinsic {
1473             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
1474             output: &::U8x128,
1475             definition: Named("llvm.hexagon.V6.vminub.128B")
1476         },
1477         "Vuh_vmin_VuhVuh128" => Intrinsic {
1478             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
1479             output: &::U16x64,
1480             definition: Named("llvm.hexagon.V6.vminuh.128B")
1481         },
1482         "Wh_vmpa_WubRb64" => Intrinsic {
1483             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
1484             output: &::I16x64,
1485             definition: Named("llvm.hexagon.V6.vmpabus")
1486         },
1487         "Wh_vmpa_WubRb128" => Intrinsic {
1488             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
1489             output: &::I16x128,
1490             definition: Named("llvm.hexagon.V6.vmpabus.128B")
1491         },
1492         "Wh_vmpaacc_WhWubRb64" => Intrinsic {
1493             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS },
1494             output: &::I16x64,
1495             definition: Named("llvm.hexagon.V6.vmpabus.acc")
1496         },
1497         "Wh_vmpaacc_WhWubRb128" => Intrinsic {
1498             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS },
1499             output: &::I16x128,
1500             definition: Named("llvm.hexagon.V6.vmpabus.acc.128B")
1501         },
1502         "Wh_vmpa_WubWb64" => Intrinsic {
1503             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS },
1504             output: &::I16x64,
1505             definition: Named("llvm.hexagon.V6.vmpabusv")
1506         },
1507         "Wh_vmpa_WubWub64" => Intrinsic {
1508             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
1509             output: &::I16x64,
1510             definition: Named("llvm.hexagon.V6.vmpabuuv")
1511         },
1512         "Wh_vmpa_WubWb128" => Intrinsic {
1513             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::I8x256]; &INPUTS },
1514             output: &::I16x128,
1515             definition: Named("llvm.hexagon.V6.vmpabusv.128B")
1516         },
1517         "Wh_vmpa_WubWub128" => Intrinsic {
1518             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS },
1519             output: &::I16x128,
1520             definition: Named("llvm.hexagon.V6.vmpabuuv.128B")
1521         },
1522         "Ww_vmpa_WhRb64" => Intrinsic {
1523             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
1524             output: &::I32x32,
1525             definition: Named("llvm.hexagon.V6.vmpahb")
1526         },
1527         "Ww_vmpa_WhRb128" => Intrinsic {
1528             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS },
1529             output: &::I32x64,
1530             definition: Named("llvm.hexagon.V6.vmpahb.128B")
1531         },
1532         "Ww_vmpaacc_WwWhRb64" => Intrinsic {
1533             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
1534             output: &::I32x32,
1535             definition: Named("llvm.hexagon.V6.vmpahb.acc")
1536         },
1537         "Ww_vmpaacc_WwWhRb128" => Intrinsic {
1538             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS },
1539             output: &::I32x64,
1540             definition: Named("llvm.hexagon.V6.vmpahb.acc.128B")
1541         },
1542         "Wh_vmpy_VbVub64" => Intrinsic {
1543             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::U8x64]; &INPUTS },
1544             output: &::I16x64,
1545             definition: Named("llvm.hexagon.V6.vmpybus")
1546         },
1547         "Ww_vmpy_VhVuh64" => Intrinsic {
1548             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U16x32]; &INPUTS },
1549             output: &::I32x32,
1550             definition: Named("llvm.hexagon.V6.vmpyhus")
1551         },
1552         "Wh_vmpy_VbVub128" => Intrinsic {
1553             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::U8x128]; &INPUTS },
1554             output: &::I16x128,
1555             definition: Named("llvm.hexagon.V6.vmpybus.128B")
1556         },
1557         "Ww_vmpy_VhVuh128" => Intrinsic {
1558             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U16x64]; &INPUTS },
1559             output: &::I32x64,
1560             definition: Named("llvm.hexagon.V6.vmpyhus.128B")
1561         },
1562         "Wh_vmpyacc_WhVbVub64" => Intrinsic {
1563             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x64, &::U8x64]; &INPUTS },
1564             output: &::I16x64,
1565             definition: Named("llvm.hexagon.V6.vmpybus.acc")
1566         },
1567         "Ww_vmpyacc_WwVhVuh64" => Intrinsic {
1568             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::U16x32]; &INPUTS },
1569             output: &::I32x32,
1570             definition: Named("llvm.hexagon.V6.vmpyhus.acc")
1571         },
1572         "Wh_vmpyacc_WhVbVub128" => Intrinsic {
1573             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x128, &::U8x128]; &INPUTS },
1574             output: &::I16x128,
1575             definition: Named("llvm.hexagon.V6.vmpybus.acc.128B")
1576         },
1577         "Ww_vmpyacc_WwVhVuh128" => Intrinsic {
1578             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::U16x64]; &INPUTS },
1579             output: &::I32x64,
1580             definition: Named("llvm.hexagon.V6.vmpyhus.acc.128B")
1581         },
1582         "Wh_vmpy_VubVb64" => Intrinsic {
1583             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::I8x64]; &INPUTS },
1584             output: &::I16x64,
1585             definition: Named("llvm.hexagon.V6.vmpybusv")
1586         },
1587         "Wh_vmpy_VubVb128" => Intrinsic {
1588             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS },
1589             output: &::I16x128,
1590             definition: Named("llvm.hexagon.V6.vmpybusv.128B")
1591         },
1592         "Wh_vmpyacc_WhVubVb64" => Intrinsic {
1593             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x64, &::I8x64]; &INPUTS },
1594             output: &::I16x64,
1595             definition: Named("llvm.hexagon.V6.vmpybusv.acc")
1596         },
1597         "Wh_vmpyacc_WhVubVb128" => Intrinsic {
1598             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x128, &::I8x128]; &INPUTS },
1599             output: &::I16x128,
1600             definition: Named("llvm.hexagon.V6.vmpybusv.acc.128B")
1601         },
1602         "Wh_vmpy_VbVb64" => Intrinsic {
1603             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
1604             output: &::I16x64,
1605             definition: Named("llvm.hexagon.V6.vmpybv")
1606         },
1607         "Wuh_vmpy_VubVub64" => Intrinsic {
1608             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
1609             output: &::U16x64,
1610             definition: Named("llvm.hexagon.V6.vmpyubv")
1611         },
1612         "Ww_vmpy_VhVh64" => Intrinsic {
1613             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1614             output: &::I32x32,
1615             definition: Named("llvm.hexagon.V6.vmpyhv")
1616         },
1617         "Wuw_vmpy_VuhVuh64" => Intrinsic {
1618             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
1619             output: &::U32x32,
1620             definition: Named("llvm.hexagon.V6.vmpyuhv")
1621         },
1622         "Wh_vmpy_VbVb128" => Intrinsic {
1623             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
1624             output: &::I16x128,
1625             definition: Named("llvm.hexagon.V6.vmpybv.128B")
1626         },
1627         "Wuh_vmpy_VubVub128" => Intrinsic {
1628             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
1629             output: &::U16x128,
1630             definition: Named("llvm.hexagon.V6.vmpyubv.128B")
1631         },
1632         "Ww_vmpy_VhVh128" => Intrinsic {
1633             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1634             output: &::I32x64,
1635             definition: Named("llvm.hexagon.V6.vmpyhv.128B")
1636         },
1637         "Wuw_vmpy_VuhVuh128" => Intrinsic {
1638             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
1639             output: &::U32x64,
1640             definition: Named("llvm.hexagon.V6.vmpyuhv.128B")
1641         },
1642         "Wh_vmpyacc_WhVbVb64" => Intrinsic {
1643             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x64, &::I8x64]; &INPUTS },
1644             output: &::I16x64,
1645             definition: Named("llvm.hexagon.V6.vmpybv.acc")
1646         },
1647         "Wuh_vmpyacc_WuhVubVub64" => Intrinsic {
1648             inputs: { static INPUTS: [&'static Type; 3] = [&::U16x64, &::U8x64, &::U8x64]; &INPUTS },
1649             output: &::U16x64,
1650             definition: Named("llvm.hexagon.V6.vmpyubv.acc")
1651         },
1652         "Ww_vmpyacc_WwVhVh64" => Intrinsic {
1653             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::I16x32]; &INPUTS },
1654             output: &::I32x32,
1655             definition: Named("llvm.hexagon.V6.vmpyhv.acc")
1656         },
1657         "Wuw_vmpyacc_WuwVuhVuh64" => Intrinsic {
1658             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x32, &::U16x32]; &INPUTS },
1659             output: &::U32x32,
1660             definition: Named("llvm.hexagon.V6.vmpyuhv.acc")
1661         },
1662         "Wh_vmpyacc_WhVbVb128" => Intrinsic {
1663             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x128, &::I8x128]; &INPUTS },
1664             output: &::I16x128,
1665             definition: Named("llvm.hexagon.V6.vmpybv.acc.128B")
1666         },
1667         "Wuh_vmpyacc_WuhVubVub128" => Intrinsic {
1668             inputs: { static INPUTS: [&'static Type; 3] = [&::U16x128, &::U8x128, &::U8x128]; &INPUTS },
1669             output: &::U16x128,
1670             definition: Named("llvm.hexagon.V6.vmpyubv.acc.128B")
1671         },
1672         "Ww_vmpyacc_WwVhVh128" => Intrinsic {
1673             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::I16x64]; &INPUTS },
1674             output: &::I32x64,
1675             definition: Named("llvm.hexagon.V6.vmpyhv.acc.128B")
1676         },
1677         "Wuw_vmpyacc_WuwVuhVuh128" => Intrinsic {
1678             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x64, &::U16x64]; &INPUTS },
1679             output: &::U32x64,
1680             definition: Named("llvm.hexagon.V6.vmpyuhv.acc.128B")
1681         },
1682         "Vw_vmpye_VwVuh64" => Intrinsic {
1683             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U16x32]; &INPUTS },
1684             output: &::I32x16,
1685             definition: Named("llvm.hexagon.V6.vmpyewuh")
1686         },
1687         "Vw_vmpye_VwVuh128" => Intrinsic {
1688             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U16x64]; &INPUTS },
1689             output: &::I32x32,
1690             definition: Named("llvm.hexagon.V6.vmpyewuh.128B")
1691         },
1692         "Ww_vmpy_VhRh64" => Intrinsic {
1693             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
1694             output: &::I32x32,
1695             definition: Named("llvm.hexagon.V6.vmpyh")
1696         },
1697         "Wuw_vmpy_VuhRuh64" => Intrinsic {
1698             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U32]; &INPUTS },
1699             output: &::U32x32,
1700             definition: Named("llvm.hexagon.V6.vmpyuh")
1701         },
1702         "Ww_vmpy_VhRh128" => Intrinsic {
1703             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
1704             output: &::I32x64,
1705             definition: Named("llvm.hexagon.V6.vmpyh.128B")
1706         },
1707         "Wuw_vmpy_VuhRuh128" => Intrinsic {
1708             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS },
1709             output: &::U32x64,
1710             definition: Named("llvm.hexagon.V6.vmpyuh.128B")
1711         },
1712         "Ww_vmpyacc_WwVhRh_sat64" => Intrinsic {
1713             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::U32]; &INPUTS },
1714             output: &::I32x32,
1715             definition: Named("llvm.hexagon.V6.vmpyhsat.acc")
1716         },
1717         "Ww_vmpyacc_WwVhRh_sat128" => Intrinsic {
1718             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::U32]; &INPUTS },
1719             output: &::I32x64,
1720             definition: Named("llvm.hexagon.V6.vmpyhsat.acc.128B")
1721         },
1722         "Vw_vmpy_VhRh_s1_rnd_sat64" => Intrinsic {
1723             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
1724             output: &::I32x16,
1725             definition: Named("llvm.hexagon.V6.vmpyhsrs")
1726         },
1727         "Vw_vmpy_VhRh_s1_rnd_sat128" => Intrinsic {
1728             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
1729             output: &::I32x32,
1730             definition: Named("llvm.hexagon.V6.vmpyhsrs.128B")
1731         },
1732         "Vw_vmpy_VhRh_s1_sat64" => Intrinsic {
1733             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
1734             output: &::I32x16,
1735             definition: Named("llvm.hexagon.V6.vmpyhss")
1736         },
1737         "Vw_vmpy_VhRh_s1_sat128" => Intrinsic {
1738             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
1739             output: &::I32x32,
1740             definition: Named("llvm.hexagon.V6.vmpyhss.128B")
1741         },
1742         "Vh_vmpy_VhVh_s1_rnd_sat64" => Intrinsic {
1743             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1744             output: &::I16x32,
1745             definition: Named("llvm.hexagon.V6.vmpyhvsrs")
1746         },
1747         "Vh_vmpy_VhVh_s1_rnd_sat128" => Intrinsic {
1748             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1749             output: &::I16x64,
1750             definition: Named("llvm.hexagon.V6.vmpyhvsrs.128B")
1751         },
1752         "Vw_vmpyieo_VhVh64" => Intrinsic {
1753             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1754             output: &::I32x16,
1755             definition: Named("llvm.hexagon.V6.vmpyieoh")
1756         },
1757         "Vw_vmpyieo_VhVh128" => Intrinsic {
1758             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1759             output: &::I32x32,
1760             definition: Named("llvm.hexagon.V6.vmpyieoh.128B")
1761         },
1762         "Vw_vmpyieacc_VwVwVh64" => Intrinsic {
1763             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::I16x32]; &INPUTS },
1764             output: &::I32x16,
1765             definition: Named("llvm.hexagon.V6.vmpyiewh.acc")
1766         },
1767         "Vw_vmpyieacc_VwVwVuh64" => Intrinsic {
1768             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U16x32]; &INPUTS },
1769             output: &::I32x16,
1770             definition: Named("llvm.hexagon.V6.vmpyiewuh.acc")
1771         },
1772         "Vw_vmpyieacc_VwVwVh128" => Intrinsic {
1773             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::I16x64]; &INPUTS },
1774             output: &::I32x32,
1775             definition: Named("llvm.hexagon.V6.vmpyiewh.acc.128B")
1776         },
1777         "Vw_vmpyieacc_VwVwVuh128" => Intrinsic {
1778             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U16x64]; &INPUTS },
1779             output: &::I32x32,
1780             definition: Named("llvm.hexagon.V6.vmpyiewuh.acc.128B")
1781         },
1782         "Vw_vmpyie_VwVuh64" => Intrinsic {
1783             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U16x32]; &INPUTS },
1784             output: &::I32x16,
1785             definition: Named("llvm.hexagon.V6.vmpyiewuh")
1786         },
1787         "Vw_vmpyie_VwVuh128" => Intrinsic {
1788             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U16x64]; &INPUTS },
1789             output: &::I32x32,
1790             definition: Named("llvm.hexagon.V6.vmpyiewuh.128B")
1791         },
1792         "Vh_vmpyi_VhVh64" => Intrinsic {
1793             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1794             output: &::I16x32,
1795             definition: Named("llvm.hexagon.V6.vmpyih")
1796         },
1797         "Vh_vmpyi_VhVh128" => Intrinsic {
1798             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
1799             output: &::I16x64,
1800             definition: Named("llvm.hexagon.V6.vmpyih.128B")
1801         },
1802         "Vh_vmpyiacc_VhVhVh64" => Intrinsic {
1803             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::I16x32]; &INPUTS },
1804             output: &::I16x32,
1805             definition: Named("llvm.hexagon.V6.vmpyih.acc")
1806         },
1807         "Vh_vmpyiacc_VhVhVh128" => Intrinsic {
1808             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::I16x64]; &INPUTS },
1809             output: &::I16x64,
1810             definition: Named("llvm.hexagon.V6.vmpyih.acc.128B")
1811         },
1812         "Vh_vmpyi_VhRb64" => Intrinsic {
1813             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS },
1814             output: &::I16x32,
1815             definition: Named("llvm.hexagon.V6.vmpyihb")
1816         },
1817         "Vw_vmpyi_VwRb64" => Intrinsic {
1818             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS },
1819             output: &::I32x16,
1820             definition: Named("llvm.hexagon.V6.vmpyiwb")
1821         },
1822         "Vh_vmpyi_VhRb128" => Intrinsic {
1823             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
1824             output: &::I16x64,
1825             definition: Named("llvm.hexagon.V6.vmpyihb.128B")
1826         },
1827         "Vw_vmpyi_VwRb128" => Intrinsic {
1828             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
1829             output: &::I32x32,
1830             definition: Named("llvm.hexagon.V6.vmpyiwb.128B")
1831         },
1832         "Vh_vmpyiacc_VhVhRb64" => Intrinsic {
1833             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS },
1834             output: &::I16x32,
1835             definition: Named("llvm.hexagon.V6.vmpyihb.acc")
1836         },
1837         "Vw_vmpyiacc_VwVwRb64" => Intrinsic {
1838             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
1839             output: &::I32x16,
1840             definition: Named("llvm.hexagon.V6.vmpyiwb.acc")
1841         },
1842         "Vh_vmpyiacc_VhVhRb128" => Intrinsic {
1843             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS },
1844             output: &::I16x64,
1845             definition: Named("llvm.hexagon.V6.vmpyihb.acc.128B")
1846         },
1847         "Vw_vmpyiacc_VwVwRb128" => Intrinsic {
1848             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
1849             output: &::I32x32,
1850             definition: Named("llvm.hexagon.V6.vmpyiwb.acc.128B")
1851         },
1852         "Vw_vmpyi_VwRh64" => Intrinsic {
1853             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS },
1854             output: &::I32x16,
1855             definition: Named("llvm.hexagon.V6.vmpyiwh")
1856         },
1857         "Vw_vmpyi_VwRh128" => Intrinsic {
1858             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
1859             output: &::I32x32,
1860             definition: Named("llvm.hexagon.V6.vmpyiwh.128B")
1861         },
1862         "Vw_vmpyiacc_VwVwRh64" => Intrinsic {
1863             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
1864             output: &::I32x16,
1865             definition: Named("llvm.hexagon.V6.vmpyiwh.acc")
1866         },
1867         "Vw_vmpyiacc_VwVwRh128" => Intrinsic {
1868             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
1869             output: &::I32x32,
1870             definition: Named("llvm.hexagon.V6.vmpyiwh.acc.128B")
1871         },
1872         "Vw_vmpyi_VwRub64" => Intrinsic {
1873             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS },
1874             output: &::I32x16,
1875             definition: Named("llvm.hexagon.V6.vmpyiwub")
1876         },
1877         "Vw_vmpyi_VwRub128" => Intrinsic {
1878             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS },
1879             output: &::I32x32,
1880             definition: Named("llvm.hexagon.V6.vmpyiwub.128B")
1881         },
1882         "Vw_vmpyiacc_VwVwRub64" => Intrinsic {
1883             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS },
1884             output: &::I32x16,
1885             definition: Named("llvm.hexagon.V6.vmpyiwub.acc")
1886         },
1887         "Vw_vmpyiacc_VwVwRub128" => Intrinsic {
1888             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS },
1889             output: &::I32x32,
1890             definition: Named("llvm.hexagon.V6.vmpyiwub.acc.128B")
1891         },
1892         "Vw_vmpyo_VwVh_s1_sat64" => Intrinsic {
1893             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS },
1894             output: &::I32x16,
1895             definition: Named("llvm.hexagon.V6.vmpyowh")
1896         },
1897         "Vw_vmpyo_VwVh_s1_sat128" => Intrinsic {
1898             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS },
1899             output: &::I32x32,
1900             definition: Named("llvm.hexagon.V6.vmpyowh.128B")
1901         },
1902         "Vw_vmpyo_VwVh_s1_rnd_sat64" => Intrinsic {
1903             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS },
1904             output: &::I32x16,
1905             definition: Named("llvm.hexagon.V6.vmpyowh.rnd")
1906         },
1907         "Vw_vmpyo_VwVh_s1_rnd_sat128" => Intrinsic {
1908             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS },
1909             output: &::I32x32,
1910             definition: Named("llvm.hexagon.V6.vmpyowh.rnd.128B")
1911         },
1912         "Vw_vmpyo_VwVh_s1_rnd_sat_shift64" => Intrinsic {
1913             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS },
1914             output: &::I32x16,
1915             definition: Named("llvm.hexagon.V6.vmpyowh.rnd.sacc")
1916         },
1917         "Vw_vmpyo_VwVh_s1_rnd_sat_shift128" => Intrinsic {
1918             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS },
1919             output: &::I32x32,
1920             definition: Named("llvm.hexagon.V6.vmpyowh.rnd.sacc.128B")
1921         },
1922         "Vw_vmpyo_VwVh_s1_sat_shift64" => Intrinsic {
1923             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS },
1924             output: &::I32x16,
1925             definition: Named("llvm.hexagon.V6.vmpyowh.sacc")
1926         },
1927         "Vw_vmpyo_VwVh_s1_sat_shift128" => Intrinsic {
1928             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS },
1929             output: &::I32x32,
1930             definition: Named("llvm.hexagon.V6.vmpyowh.sacc.128B")
1931         },
1932         "Vw_vmpyio_VwVh64" => Intrinsic {
1933             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS },
1934             output: &::I32x16,
1935             definition: Named("llvm.hexagon.V6.vmpyiowh")
1936         },
1937         "Vw_vmpyio_VwVh128" => Intrinsic {
1938             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS },
1939             output: &::I32x32,
1940             definition: Named("llvm.hexagon.V6.vmpyiowh.128B")
1941         },
1942         "Wuh_vmpy_VubRub64" => Intrinsic {
1943             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
1944             output: &::U16x64,
1945             definition: Named("llvm.hexagon.V6.vmpyub")
1946         },
1947         "Wuh_vmpy_VubRub128" => Intrinsic {
1948             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
1949             output: &::U16x128,
1950             definition: Named("llvm.hexagon.V6.vmpyub.128B")
1951         },
1952         "Wuh_vmpyacc_WuhVubRub64" => Intrinsic {
1953             inputs: { static INPUTS: [&'static Type; 3] = [&::U16x64, &::U8x64, &::U32]; &INPUTS },
1954             output: &::U16x64,
1955             definition: Named("llvm.hexagon.V6.vmpyub.acc")
1956         },
1957         "Wuw_vmpyacc_WuwVuhRuh64" => Intrinsic {
1958             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x32, &::U32]; &INPUTS },
1959             output: &::U32x32,
1960             definition: Named("llvm.hexagon.V6.vmpyuh.acc")
1961         },
1962         "Wuh_vmpyacc_WuhVubRub128" => Intrinsic {
1963             inputs: { static INPUTS: [&'static Type; 3] = [&::U16x128, &::U8x128, &::U32]; &INPUTS },
1964             output: &::U16x128,
1965             definition: Named("llvm.hexagon.V6.vmpyub.acc.128B")
1966         },
1967         "Wuw_vmpyacc_WuwVuhRuh128" => Intrinsic {
1968             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x64, &::U32]; &INPUTS },
1969             output: &::U32x64,
1970             definition: Named("llvm.hexagon.V6.vmpyuh.acc.128B")
1971         },
1972         "Vuw_vmux_QVV64" => Intrinsic {
1973             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U32x16, &::U32x16]; &INPUTS },
1974             output: &::U32x16,
1975             definition: Named("llvm.hexagon.V6.vmux")
1976         },
1977         "Vuw_vmux_QVV128" => Intrinsic {
1978             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U32x32, &::U32x32]; &INPUTS },
1979             output: &::U32x32,
1980             definition: Named("llvm.hexagon.V6.vmux.128B")
1981         },
1982         "Vh_vnavg_VhVh64" => Intrinsic {
1983             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
1984             output: &::I16x32,
1985             definition: Named("llvm.hexagon.V6.vnavgh")
1986         },
1987         "Vuh_vnavg_VuhVuh64" => Intrinsic {
1988             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
1989             output: &::U16x32,
1990             definition: Named("llvm.hexagon.V6.vnavguh")
1991         },
1992         "Vw_vnavg_VwVw64" => Intrinsic {
1993             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
1994             output: &::I32x16,
1995             definition: Named("llvm.hexagon.V6.vnavgw")
1996         },
1997         "Vuw_vnavg_VuwVuw64" => Intrinsic {
1998             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32x16]; &INPUTS },
1999             output: &::U32x16,
2000             definition: Named("llvm.hexagon.V6.vnavguw")
2001         },
2002         "Vh_vnavg_VhVh128" => Intrinsic {
2003             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2004             output: &::I16x64,
2005             definition: Named("llvm.hexagon.V6.vnavgh.128B")
2006         },
2007         "Vuh_vnavg_VuhVuh128" => Intrinsic {
2008             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
2009             output: &::U16x64,
2010             definition: Named("llvm.hexagon.V6.vnavguh.128B")
2011         },
2012         "Vw_vnavg_VwVw128" => Intrinsic {
2013             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2014             output: &::I32x32,
2015             definition: Named("llvm.hexagon.V6.vnavgw.128B")
2016         },
2017         "Vuw_vnavg_VuwVuw128" => Intrinsic {
2018             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32x32]; &INPUTS },
2019             output: &::U32x32,
2020             definition: Named("llvm.hexagon.V6.vnavguw.128B")
2021         },
2022         "Vub_vnavg_VubVub64" => Intrinsic {
2023             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
2024             output: &::U8x64,
2025             definition: Named("llvm.hexagon.V6.vnavgub")
2026         },
2027         "Vub_vnavg_VubVub128" => Intrinsic {
2028             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
2029             output: &::U8x128,
2030             definition: Named("llvm.hexagon.V6.vnavgub.128B")
2031         },
2032         "Vh_vnormamt_Vh64" => Intrinsic {
2033             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
2034             output: &::I16x32,
2035             definition: Named("llvm.hexagon.V6.vnormamth")
2036         },
2037         "Vw_vnormamt_Vw64" => Intrinsic {
2038             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS },
2039             output: &::I32x16,
2040             definition: Named("llvm.hexagon.V6.vnormamtw")
2041         },
2042         "Vh_vnormamt_Vh128" => Intrinsic {
2043             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
2044             output: &::I16x64,
2045             definition: Named("llvm.hexagon.V6.vnormamth.128B")
2046         },
2047         "Vw_vnormamt_Vw128" => Intrinsic {
2048             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS },
2049             output: &::I32x32,
2050             definition: Named("llvm.hexagon.V6.vnormamtw.128B")
2051         },
2052         "V_vnot_VV64" => Intrinsic {
2053             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS },
2054             output: &::U16x32,
2055             definition: Named("llvm.hexagon.V6.vnot")
2056         },
2057         "V_vnot_VV128" => Intrinsic {
2058             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS },
2059             output: &::U16x64,
2060             definition: Named("llvm.hexagon.V6.vnot.128B")
2061         },
2062         "V_vor_VV64" => Intrinsic {
2063             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
2064             output: &::U16x32,
2065             definition: Named("llvm.hexagon.V6.vor")
2066         },
2067         "V_vor_VV128" => Intrinsic {
2068             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
2069             output: &::U16x64,
2070             definition: Named("llvm.hexagon.V6.vor.128B")
2071         },
2072         "Vb_vpacke_VhVh64" => Intrinsic {
2073             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2074             output: &::I8x64,
2075             definition: Named("llvm.hexagon.V6.vpackhe")
2076         },
2077         "Vh_vpacke_VwVw64" => Intrinsic {
2078             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2079             output: &::I16x32,
2080             definition: Named("llvm.hexagon.V6.vpackwe")
2081         },
2082         "Vb_vpacke_VhVh128" => Intrinsic {
2083             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2084             output: &::I8x128,
2085             definition: Named("llvm.hexagon.V6.vpackhe.128B")
2086         },
2087         "Vh_vpacke_VwVw128" => Intrinsic {
2088             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2089             output: &::I16x64,
2090             definition: Named("llvm.hexagon.V6.vpackwe.128B")
2091         },
2092         "Vb_vpacko_VhVh64" => Intrinsic {
2093             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2094             output: &::I8x64,
2095             definition: Named("llvm.hexagon.V6.vpackho")
2096         },
2097         "Vh_vpacko_VwVw64" => Intrinsic {
2098             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2099             output: &::I16x32,
2100             definition: Named("llvm.hexagon.V6.vpackwo")
2101         },
2102         "Vb_vpacko_VhVh128" => Intrinsic {
2103             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2104             output: &::I8x128,
2105             definition: Named("llvm.hexagon.V6.vpackho.128B")
2106         },
2107         "Vh_vpacko_VwVw128" => Intrinsic {
2108             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2109             output: &::I16x64,
2110             definition: Named("llvm.hexagon.V6.vpackwo.128B")
2111         },
2112         "Vb_vpack_VhVh_sat64" => Intrinsic {
2113             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2114             output: &::I8x64,
2115             definition: Named("llvm.hexagon.V6.vpackhb.sat")
2116         },
2117         "Vub_vpack_VhVh_sat64" => Intrinsic {
2118             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2119             output: &::U8x64,
2120             definition: Named("llvm.hexagon.V6.vpackhub.sat")
2121         },
2122         "Vh_vpack_VwVw_sat64" => Intrinsic {
2123             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2124             output: &::I16x32,
2125             definition: Named("llvm.hexagon.V6.vpackwh.sat")
2126         },
2127         "Vuh_vpack_VwVw_sat64" => Intrinsic {
2128             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2129             output: &::U16x32,
2130             definition: Named("llvm.hexagon.V6.vpackwuh.sat")
2131         },
2132         "Vb_vpack_VhVh_sat128" => Intrinsic {
2133             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2134             output: &::I8x128,
2135             definition: Named("llvm.hexagon.V6.vpackhb.sat.128B")
2136         },
2137         "Vub_vpack_VhVh_sat128" => Intrinsic {
2138             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2139             output: &::U8x128,
2140             definition: Named("llvm.hexagon.V6.vpackhub.sat.128B")
2141         },
2142         "Vh_vpack_VwVw_sat128" => Intrinsic {
2143             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2144             output: &::I16x64,
2145             definition: Named("llvm.hexagon.V6.vpackwh.sat.128B")
2146         },
2147         "Vuh_vpack_VwVw_sat128" => Intrinsic {
2148             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2149             output: &::U16x64,
2150             definition: Named("llvm.hexagon.V6.vpackwuh.sat.128B")
2151         },
2152         "Vh_vpopcount_Vh64" => Intrinsic {
2153             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
2154             output: &::I16x32,
2155             definition: Named("llvm.hexagon.V6.vpopcounth")
2156         },
2157         "Vh_vpopcount_Vh128" => Intrinsic {
2158             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
2159             output: &::I16x64,
2160             definition: Named("llvm.hexagon.V6.vpopcounth.128B")
2161         },
2162         "V_vrdelta_VV64" => Intrinsic {
2163             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
2164             output: &::U8x64,
2165             definition: Named("llvm.hexagon.V6.vrdelta")
2166         },
2167         "V_vrdelta_VV128" => Intrinsic {
2168             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
2169             output: &::U8x128,
2170             definition: Named("llvm.hexagon.V6.vrdelta.128B")
2171         },
2172         "Vw_vrmpy_VubRb64" => Intrinsic {
2173             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
2174             output: &::I32x16,
2175             definition: Named("llvm.hexagon.V6.vrmpybus")
2176         },
2177         "Vw_vrmpy_VubRb128" => Intrinsic {
2178             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2179             output: &::I32x32,
2180             definition: Named("llvm.hexagon.V6.vrmpybus.128B")
2181         },
2182         "Vw_vrmpyacc_VwVubRb64" => Intrinsic {
2183             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::U8x64, &::U32]; &INPUTS },
2184             output: &::I32x16,
2185             definition: Named("llvm.hexagon.V6.vrmpybus.acc")
2186         },
2187         "Vw_vrmpyacc_VwVubRb128" => Intrinsic {
2188             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::U32]; &INPUTS },
2189             output: &::I32x32,
2190             definition: Named("llvm.hexagon.V6.vrmpybus.acc.128B")
2191         },
2192         "Ww_vrmpy_WubRbI64" => Intrinsic {
2193             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2194             output: &::I32x32,
2195             definition: Named("llvm.hexagon.V6.vrmpybusi")
2196         },
2197         "Ww_vrmpy_WubRbI128" => Intrinsic {
2198             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
2199             output: &::I32x64,
2200             definition: Named("llvm.hexagon.V6.vrmpybusi.128B")
2201         },
2202         "Ww_vrmpyacc_WwWubRbI64" => Intrinsic {
2203             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::U32]; &INPUTS },
2204             output: &::I32x32,
2205             definition: Named("llvm.hexagon.V6.vrmpybusi.acc")
2206         },
2207         "Ww_vrmpyacc_WwWubRbI128" => Intrinsic {
2208             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::U8x256, &::U32]; &INPUTS },
2209             output: &::I32x64,
2210             definition: Named("llvm.hexagon.V6.vrmpybusi.acc.128B")
2211         },
2212         "Vw_vrmpy_VubVb64" => Intrinsic {
2213             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::I8x64]; &INPUTS },
2214             output: &::I32x16,
2215             definition: Named("llvm.hexagon.V6.vrmpybusv")
2216         },
2217         "Vw_vrmpy_VubVb128" => Intrinsic {
2218             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS },
2219             output: &::I32x32,
2220             definition: Named("llvm.hexagon.V6.vrmpybusv.128B")
2221         },
2222         "Vw_vrmpyacc_VwVubVb64" => Intrinsic {
2223             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::U8x64, &::I8x64]; &INPUTS },
2224             output: &::I32x16,
2225             definition: Named("llvm.hexagon.V6.vrmpybusv.acc")
2226         },
2227         "Vw_vrmpyacc_VwVubVb128" => Intrinsic {
2228             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::I8x128]; &INPUTS },
2229             output: &::I32x32,
2230             definition: Named("llvm.hexagon.V6.vrmpybusv.acc.128B")
2231         },
2232         "Vw_vrmpy_VbVb64" => Intrinsic {
2233             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
2234             output: &::I32x16,
2235             definition: Named("llvm.hexagon.V6.vrmpybv")
2236         },
2237         "Vuw_vrmpy_VubVub64" => Intrinsic {
2238             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
2239             output: &::U32x16,
2240             definition: Named("llvm.hexagon.V6.vrmpyubv")
2241         },
2242         "Vw_vrmpy_VbVb128" => Intrinsic {
2243             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2244             output: &::I32x32,
2245             definition: Named("llvm.hexagon.V6.vrmpybv.128B")
2246         },
2247         "Vuw_vrmpy_VubVub128" => Intrinsic {
2248             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
2249             output: &::U32x32,
2250             definition: Named("llvm.hexagon.V6.vrmpyubv.128B")
2251         },
2252         "Vw_vrmpyacc_VwVbVb64" => Intrinsic {
2253             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I8x64, &::I8x64]; &INPUTS },
2254             output: &::I32x16,
2255             definition: Named("llvm.hexagon.V6.vrmpywv.acc")
2256         },
2257         "Vuw_vrmpyacc_VuwVubVub64" => Intrinsic {
2258             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x16, &::U8x64, &::U8x64]; &INPUTS },
2259             output: &::U32x16,
2260             definition: Named("llvm.hexagon.V6.vrmpyuwv.acc")
2261         },
2262         "Vw_vrmpyacc_VwVbVb128" => Intrinsic {
2263             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I8x128, &::I8x128]; &INPUTS },
2264             output: &::I32x32,
2265             definition: Named("llvm.hexagon.V6.vrmpywv.acc.128B")
2266         },
2267         "Vuw_vrmpyacc_VuwVubVub128" => Intrinsic {
2268             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U8x128]; &INPUTS },
2269             output: &::U32x32,
2270             definition: Named("llvm.hexagon.V6.vrmpyuwv.acc.128B")
2271         },
2272         "Vuw_vrmpy_VubRub64" => Intrinsic {
2273             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
2274             output: &::U32x16,
2275             definition: Named("llvm.hexagon.V6.vrmpyub")
2276         },
2277         "Vuw_vrmpy_VubRub128" => Intrinsic {
2278             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2279             output: &::U32x32,
2280             definition: Named("llvm.hexagon.V6.vrmpyub.128B")
2281         },
2282         "Vuw_vrmpyacc_VuwVubRub64" => Intrinsic {
2283             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x16, &::U8x64, &::U32]; &INPUTS },
2284             output: &::U32x16,
2285             definition: Named("llvm.hexagon.V6.vrmpyub.acc")
2286         },
2287         "Vuw_vrmpyacc_VuwVubRub128" => Intrinsic {
2288             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS },
2289             output: &::U32x32,
2290             definition: Named("llvm.hexagon.V6.vrmpyub.acc.128B")
2291         },
2292         "Wuw_vrmpy_WubRubI64" => Intrinsic {
2293             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2294             output: &::U32x32,
2295             definition: Named("llvm.hexagon.V6.vrmpyubi")
2296         },
2297         "Wuw_vrmpy_WubRubI128" => Intrinsic {
2298             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
2299             output: &::U32x64,
2300             definition: Named("llvm.hexagon.V6.vrmpyubi.128B")
2301         },
2302         "Wuw_vrmpyacc_WuwWubRubI64" => Intrinsic {
2303             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS },
2304             output: &::U32x32,
2305             definition: Named("llvm.hexagon.V6.vrmpyubi.acc")
2306         },
2307         "Wuw_vrmpyacc_WuwWubRubI128" => Intrinsic {
2308             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U8x256, &::U32]; &INPUTS },
2309             output: &::U32x64,
2310             definition: Named("llvm.hexagon.V6.vrmpyubi.acc.128B")
2311         },
2312         "V_vror_VR64" => Intrinsic {
2313             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS },
2314             output: &::U8x64,
2315             definition: Named("llvm.hexagon.V6.vror")
2316         },
2317         "V_vror_VR128" => Intrinsic {
2318             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2319             output: &::U8x128,
2320             definition: Named("llvm.hexagon.V6.vror.128B")
2321         },
2322         "Vb_vround_VhVh_sat64" => Intrinsic {
2323             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2324             output: &::I8x64,
2325             definition: Named("llvm.hexagon.V6.vroundhb")
2326         },
2327         "Vub_vround_VhVh_sat64" => Intrinsic {
2328             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2329             output: &::U8x64,
2330             definition: Named("llvm.hexagon.V6.vroundhub")
2331         },
2332         "Vh_vround_VwVw_sat64" => Intrinsic {
2333             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2334             output: &::I16x32,
2335             definition: Named("llvm.hexagon.V6.vroundwh")
2336         },
2337         "Vuh_vround_VwVw_sat64" => Intrinsic {
2338             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2339             output: &::U16x32,
2340             definition: Named("llvm.hexagon.V6.vroundwuh")
2341         },
2342         "Vb_vround_VhVh_sat128" => Intrinsic {
2343             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2344             output: &::I8x128,
2345             definition: Named("llvm.hexagon.V6.vroundhb.128B")
2346         },
2347         "Vub_vround_VhVh_sat128" => Intrinsic {
2348             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2349             output: &::U8x128,
2350             definition: Named("llvm.hexagon.V6.vroundhub.128B")
2351         },
2352         "Vh_vround_VwVw_sat128" => Intrinsic {
2353             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2354             output: &::I16x64,
2355             definition: Named("llvm.hexagon.V6.vroundwh.128B")
2356         },
2357         "Vuh_vround_VwVw_sat128" => Intrinsic {
2358             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2359             output: &::U16x64,
2360             definition: Named("llvm.hexagon.V6.vroundwuh.128B")
2361         },
2362         "Wuw_vrsad_WubRubI64" => Intrinsic {
2363             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2364             output: &::U32x32,
2365             definition: Named("llvm.hexagon.V6.vrsadubi")
2366         },
2367         "Wuw_vrsad_WubRubI128" => Intrinsic {
2368             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
2369             output: &::U32x64,
2370             definition: Named("llvm.hexagon.V6.vrsadubi.128B")
2371         },
2372         "Wuw_vrsadacc_WuwWubRubI64" => Intrinsic {
2373             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS },
2374             output: &::U32x32,
2375             definition: Named("llvm.hexagon.V6.vrsadubi.acc")
2376         },
2377         "Wuw_vrsadacc_WuwWubRubI128" => Intrinsic {
2378             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U8x256, &::U32]; &INPUTS },
2379             output: &::U32x64,
2380             definition: Named("llvm.hexagon.V6.vrsadubi.acc.128B")
2381         },
2382         "Vub_vsat_VhVh64" => Intrinsic {
2383             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2384             output: &::U8x64,
2385             definition: Named("llvm.hexagon.V6.vsathub")
2386         },
2387         "Vub_vsat_VhVh128" => Intrinsic {
2388             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2389             output: &::U8x128,
2390             definition: Named("llvm.hexagon.V6.vsathub.128B")
2391         },
2392         "Vh_vsat_VwVw64" => Intrinsic {
2393             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2394             output: &::I16x32,
2395             definition: Named("llvm.hexagon.V6.vsatwh")
2396         },
2397         "Vh_vsat_VwVw128" => Intrinsic {
2398             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2399             output: &::I16x64,
2400             definition: Named("llvm.hexagon.V6.vsatwh.128B")
2401         },
2402         "Wh_vsxt_Vb64" => Intrinsic {
2403             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS },
2404             output: &::I16x64,
2405             definition: Named("llvm.hexagon.V6.vsb")
2406         },
2407         "Ww_vsxt_Vh64" => Intrinsic {
2408             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
2409             output: &::I32x32,
2410             definition: Named("llvm.hexagon.V6.vsh")
2411         },
2412         "Wh_vsxt_Vb128" => Intrinsic {
2413             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS },
2414             output: &::I16x128,
2415             definition: Named("llvm.hexagon.V6.vsb.128B")
2416         },
2417         "Ww_vsxt_Vh128" => Intrinsic {
2418             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
2419             output: &::I32x64,
2420             definition: Named("llvm.hexagon.V6.vsh.128B")
2421         },
2422         "Wuh_vzxt_Vub64" => Intrinsic {
2423             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x64]; &INPUTS },
2424             output: &::U16x64,
2425             definition: Named("llvm.hexagon.V6.vzb")
2426         },
2427         "Wuw_vzxt_Vuh64" => Intrinsic {
2428             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS },
2429             output: &::U32x32,
2430             definition: Named("llvm.hexagon.V6.vzh")
2431         },
2432         "Wuh_vzxt_Vub128" => Intrinsic {
2433             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x128]; &INPUTS },
2434             output: &::U16x128,
2435             definition: Named("llvm.hexagon.V6.vzb.128B")
2436         },
2437         "Wuw_vzxt_Vuh128" => Intrinsic {
2438             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS },
2439             output: &::U32x64,
2440             definition: Named("llvm.hexagon.V6.vzh.128B")
2441         },
2442         "Vb_condacc_QVbVb64" => Intrinsic {
2443             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
2444             output: &::I8x64,
2445             definition: Named("llvm.hexagon.V6.vaddbq")
2446         },
2447         "Vh_condacc_QVhVh64" => Intrinsic {
2448             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
2449             output: &::I16x32,
2450             definition: Named("llvm.hexagon.V6.vaddhq")
2451         },
2452         "Vw_condacc_QVwVw64" => Intrinsic {
2453             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
2454             output: &::I32x16,
2455             definition: Named("llvm.hexagon.V6.vaddwq")
2456         },
2457         "Vb_condacc_QVbVb128" => Intrinsic {
2458             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
2459             output: &::I8x128,
2460             definition: Named("llvm.hexagon.V6.vaddbq.128B")
2461         },
2462         "Vh_condacc_QVhVh128" => Intrinsic {
2463             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
2464             output: &::I16x64,
2465             definition: Named("llvm.hexagon.V6.vaddhq.128B")
2466         },
2467         "Vw_condacc_QVwVw128" => Intrinsic {
2468             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
2469             output: &::I32x32,
2470             definition: Named("llvm.hexagon.V6.vaddwq.128B")
2471         },
2472         "Vb_condacc_QnVbVb64" => Intrinsic {
2473             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
2474             output: &::I8x64,
2475             definition: Named("llvm.hexagon.V6.vaddbnq")
2476         },
2477         "Vh_condacc_QnVhVh64" => Intrinsic {
2478             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
2479             output: &::I16x32,
2480             definition: Named("llvm.hexagon.V6.vaddhnq")
2481         },
2482         "Vw_condacc_QnVwVw64" => Intrinsic {
2483             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
2484             output: &::I32x16,
2485             definition: Named("llvm.hexagon.V6.vaddwnq")
2486         },
2487         "Vb_condacc_QnVbVb128" => Intrinsic {
2488             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
2489             output: &::I8x128,
2490             definition: Named("llvm.hexagon.V6.vaddbnq.128B")
2491         },
2492         "Vh_condacc_QnVhVh128" => Intrinsic {
2493             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
2494             output: &::I16x64,
2495             definition: Named("llvm.hexagon.V6.vaddhnq.128B")
2496         },
2497         "Vw_condacc_QnVwVw128" => Intrinsic {
2498             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
2499             output: &::I32x32,
2500             definition: Named("llvm.hexagon.V6.vaddwnq.128B")
2501         },
2502         "Vb_condnac_QVbVb64" => Intrinsic {
2503             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
2504             output: &::I8x64,
2505             definition: Named("llvm.hexagon.V6.vsubbq")
2506         },
2507         "Vh_condnac_QVhVh64" => Intrinsic {
2508             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
2509             output: &::I16x32,
2510             definition: Named("llvm.hexagon.V6.vsubhq")
2511         },
2512         "Vw_condnac_QVwVw64" => Intrinsic {
2513             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
2514             output: &::I32x16,
2515             definition: Named("llvm.hexagon.V6.vsubwq")
2516         },
2517         "Vb_condnac_QVbVb128" => Intrinsic {
2518             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
2519             output: &::I8x128,
2520             definition: Named("llvm.hexagon.V6.vsubbq.128B")
2521         },
2522         "Vh_condnac_QVhVh128" => Intrinsic {
2523             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
2524             output: &::I16x64,
2525             definition: Named("llvm.hexagon.V6.vsubhq.128B")
2526         },
2527         "Vw_condnac_QVwVw128" => Intrinsic {
2528             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
2529             output: &::I32x32,
2530             definition: Named("llvm.hexagon.V6.vsubwq.128B")
2531         },
2532         "Vb_condnac_QnVbVb64" => Intrinsic {
2533             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS },
2534             output: &::I8x64,
2535             definition: Named("llvm.hexagon.V6.vsubbnq")
2536         },
2537         "Vh_condnac_QnVhVh64" => Intrinsic {
2538             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS },
2539             output: &::I16x32,
2540             definition: Named("llvm.hexagon.V6.vsubhnq")
2541         },
2542         "Vw_condnac_QnVwVw64" => Intrinsic {
2543             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS },
2544             output: &::I32x16,
2545             definition: Named("llvm.hexagon.V6.vsubwnq")
2546         },
2547         "Vb_condnac_QnVbVb128" => Intrinsic {
2548             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS },
2549             output: &::I8x128,
2550             definition: Named("llvm.hexagon.V6.vsubbnq.128B")
2551         },
2552         "Vh_condnac_QnVhVh128" => Intrinsic {
2553             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS },
2554             output: &::I16x64,
2555             definition: Named("llvm.hexagon.V6.vsubhnq.128B")
2556         },
2557         "Vw_condnac_QnVwVw128" => Intrinsic {
2558             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS },
2559             output: &::I32x32,
2560             definition: Named("llvm.hexagon.V6.vsubwnq.128B")
2561         },
2562         "Vh_vshuffe_VhVh64" => Intrinsic {
2563             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2564             output: &::I16x32,
2565             definition: Named("llvm.hexagon.V6.vshufeh")
2566         },
2567         "Vh_vshuffe_VhVh128" => Intrinsic {
2568             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2569             output: &::I16x64,
2570             definition: Named("llvm.hexagon.V6.vshufeh.128B")
2571         },
2572         "Vh_vshuffo_VhVh64" => Intrinsic {
2573             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2574             output: &::I16x32,
2575             definition: Named("llvm.hexagon.V6.vshufoh")
2576         },
2577         "Vh_vshuffo_VhVh128" => Intrinsic {
2578             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2579             output: &::I16x64,
2580             definition: Named("llvm.hexagon.V6.vshufoh.128B")
2581         },
2582         "Vb_vshuff_Vb64" => Intrinsic {
2583             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS },
2584             output: &::I8x64,
2585             definition: Named("llvm.hexagon.V6.vshuffb")
2586         },
2587         "Vh_vshuff_Vh64" => Intrinsic {
2588             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
2589             output: &::I16x32,
2590             definition: Named("llvm.hexagon.V6.vshuffh")
2591         },
2592         "Vb_vshuff_Vb128" => Intrinsic {
2593             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS },
2594             output: &::I8x128,
2595             definition: Named("llvm.hexagon.V6.vshuffb.128B")
2596         },
2597         "Vh_vshuff_Vh128" => Intrinsic {
2598             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
2599             output: &::I16x64,
2600             definition: Named("llvm.hexagon.V6.vshuffh.128B")
2601         },
2602         "Vb_vshuffe_VbVb64" => Intrinsic {
2603             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
2604             output: &::I8x64,
2605             definition: Named("llvm.hexagon.V6.vshuffeb")
2606         },
2607         "Vb_vshuffe_VbVb128" => Intrinsic {
2608             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2609             output: &::I8x128,
2610             definition: Named("llvm.hexagon.V6.vshuffeb.128B")
2611         },
2612         "Vb_vshuffo_VbVb64" => Intrinsic {
2613             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
2614             output: &::I8x64,
2615             definition: Named("llvm.hexagon.V6.vshuffob")
2616         },
2617         "Vb_vshuffo_VbVb128" => Intrinsic {
2618             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2619             output: &::I8x128,
2620             definition: Named("llvm.hexagon.V6.vshuffob.128B")
2621         },
2622         "Vb_vshuffoe_VbVb64" => Intrinsic {
2623             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
2624             output: &::I8x64,
2625             definition: Named("llvm.hexagon.V6.vshuffoeb")
2626         },
2627         "Vh_vshuffoe_VhVh64" => Intrinsic {
2628             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2629             output: &::I16x32,
2630             definition: Named("llvm.hexagon.V6.vshuffoeh")
2631         },
2632         "Vb_vshuffoe_VbVb128" => Intrinsic {
2633             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2634             output: &::I8x128,
2635             definition: Named("llvm.hexagon.V6.vshuffoeb.128B")
2636         },
2637         "Vh_vshuffoe_VhVh128" => Intrinsic {
2638             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2639             output: &::I16x64,
2640             definition: Named("llvm.hexagon.V6.vshuffoeh.128B")
2641         },
2642         "W_vshuff_VVR64" => Intrinsic {
2643             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS },
2644             output: &::U8x128,
2645             definition: Named("llvm.hexagon.V6.vshufvvd")
2646         },
2647         "W_vshuff_VVR128" => Intrinsic {
2648             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS },
2649             output: &::U8x256,
2650             definition: Named("llvm.hexagon.V6.vshufvvd.128B")
2651         },
2652         "Vb_vsub_VbVb64" => Intrinsic {
2653             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS },
2654             output: &::I8x64,
2655             definition: Named("llvm.hexagon.V6.vsubb")
2656         },
2657         "Vh_vsub_VhVh64" => Intrinsic {
2658             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2659             output: &::I16x32,
2660             definition: Named("llvm.hexagon.V6.vsubh")
2661         },
2662         "Vw_vsub_VwVw64" => Intrinsic {
2663             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2664             output: &::I32x16,
2665             definition: Named("llvm.hexagon.V6.vsubw")
2666         },
2667         "Vb_vsub_VbVb128" => Intrinsic {
2668             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2669             output: &::I8x128,
2670             definition: Named("llvm.hexagon.V6.vsubb.128B")
2671         },
2672         "Vh_vsub_VhVh128" => Intrinsic {
2673             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2674             output: &::I16x64,
2675             definition: Named("llvm.hexagon.V6.vsubh.128B")
2676         },
2677         "Vw_vsub_VwVw128" => Intrinsic {
2678             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2679             output: &::I32x32,
2680             definition: Named("llvm.hexagon.V6.vsubw.128B")
2681         },
2682         "Vh_vsub_VhVh_sat64" => Intrinsic {
2683             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS },
2684             output: &::I16x32,
2685             definition: Named("llvm.hexagon.V6.vsubhsat")
2686         },
2687         "Vw_vsub_VwVw_sat64" => Intrinsic {
2688             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS },
2689             output: &::I32x16,
2690             definition: Named("llvm.hexagon.V6.vsubwsat")
2691         },
2692         "Vh_vsub_VhVh_sat128" => Intrinsic {
2693             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2694             output: &::I16x64,
2695             definition: Named("llvm.hexagon.V6.vsubhsat.128B")
2696         },
2697         "Vw_vsub_VwVw_sat128" => Intrinsic {
2698             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2699             output: &::I32x32,
2700             definition: Named("llvm.hexagon.V6.vsubwsat.128B")
2701         },
2702         "Vub_vsub_VubVub_sat64" => Intrinsic {
2703             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS },
2704             output: &::U8x64,
2705             definition: Named("llvm.hexagon.V6.vsububsat")
2706         },
2707         "Vuh_vsub_VuhVuh_sat64" => Intrinsic {
2708             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
2709             output: &::U16x32,
2710             definition: Named("llvm.hexagon.V6.vsubuhsat")
2711         },
2712         "Vub_vsub_VubVub_sat128" => Intrinsic {
2713             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
2714             output: &::U8x128,
2715             definition: Named("llvm.hexagon.V6.vsububsat.128B")
2716         },
2717         "Vuh_vsub_VuhVuh_sat128" => Intrinsic {
2718             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
2719             output: &::U16x64,
2720             definition: Named("llvm.hexagon.V6.vsubuhsat.128B")
2721         },
2722         "Wb_vsub_WbWb64" => Intrinsic {
2723             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS },
2724             output: &::I8x128,
2725             definition: Named("llvm.hexagon.V6.vsubb.dv")
2726         },
2727         "Wh_vsub_WhWh64" => Intrinsic {
2728             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2729             output: &::I16x64,
2730             definition: Named("llvm.hexagon.V6.vsubh.dv")
2731         },
2732         "Ww_vsub_WwWw64" => Intrinsic {
2733             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2734             output: &::I32x32,
2735             definition: Named("llvm.hexagon.V6.vsubw.dv")
2736         },
2737         "Wb_vsub_WbWb128" => Intrinsic {
2738             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::I8x256]; &INPUTS },
2739             output: &::I8x256,
2740             definition: Named("llvm.hexagon.V6.vsubb.dv.128B")
2741         },
2742         "Wh_vsub_WhWh128" => Intrinsic {
2743             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS },
2744             output: &::I16x128,
2745             definition: Named("llvm.hexagon.V6.vsubh.dv.128B")
2746         },
2747         "Ww_vsub_WwWw128" => Intrinsic {
2748             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS },
2749             output: &::I32x64,
2750             definition: Named("llvm.hexagon.V6.vsubw.dv.128B")
2751         },
2752         "Wh_vsub_WhWh_sat64" => Intrinsic {
2753             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS },
2754             output: &::I16x64,
2755             definition: Named("llvm.hexagon.V6.vsubhsat.dv")
2756         },
2757         "Ww_vsub_WwWw_sat64" => Intrinsic {
2758             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS },
2759             output: &::I32x32,
2760             definition: Named("llvm.hexagon.V6.vsubwsat.dv")
2761         },
2762         "Wh_vsub_WhWh_sat128" => Intrinsic {
2763             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS },
2764             output: &::I16x128,
2765             definition: Named("llvm.hexagon.V6.vsubhsat.dv.128B")
2766         },
2767         "Ww_vsub_WwWw_sat128" => Intrinsic {
2768             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS },
2769             output: &::I32x64,
2770             definition: Named("llvm.hexagon.V6.vsubwsat.dv.128B")
2771         },
2772         "Wub_vsub_WubWub_sat64" => Intrinsic {
2773             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS },
2774             output: &::U8x128,
2775             definition: Named("llvm.hexagon.V6.vsububsat.dv")
2776         },
2777         "Wuh_vsub_WuhWuh_sat64" => Intrinsic {
2778             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
2779             output: &::U16x64,
2780             definition: Named("llvm.hexagon.V6.vsubuhsat.dv")
2781         },
2782         "Wub_vsub_WubWub_sat128" => Intrinsic {
2783             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS },
2784             output: &::U8x256,
2785             definition: Named("llvm.hexagon.V6.vsububsat.dv.128B")
2786         },
2787         "Wuh_vsub_WuhWuh_sat128" => Intrinsic {
2788             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U16x128]; &INPUTS },
2789             output: &::U16x128,
2790             definition: Named("llvm.hexagon.V6.vsubuhsat.dv.128B")
2791         },
2792         "W_vswap_QVV64" => Intrinsic {
2793             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS },
2794             output: &::U8x128,
2795             definition: Named("llvm.hexagon.V6.vswap")
2796         },
2797         "W_vswap_QVV128" => Intrinsic {
2798             inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS },
2799             output: &::U8x256,
2800             definition: Named("llvm.hexagon.V6.vswap.128B")
2801         },
2802         "Wh_vtmpy_WbRb64" => Intrinsic {
2803             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::U32]; &INPUTS },
2804             output: &::I16x64,
2805             definition: Named("llvm.hexagon.V6.vtmpyb")
2806         },
2807         "Wh_vtmpy_WbRb128" => Intrinsic {
2808             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::U32]; &INPUTS },
2809             output: &::I16x128,
2810             definition: Named("llvm.hexagon.V6.vtmpyb.128B")
2811         },
2812         "Wh_vtmpyacc_WhWbRb64" => Intrinsic {
2813             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x128, &::U32]; &INPUTS },
2814             output: &::I16x64,
2815             definition: Named("llvm.hexagon.V6.vtmpyb.acc")
2816         },
2817         "Wh_vtmpyacc_WhWbRb128" => Intrinsic {
2818             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x256, &::U32]; &INPUTS },
2819             output: &::I16x128,
2820             definition: Named("llvm.hexagon.V6.vtmpyb.acc.128B")
2821         },
2822         "Wh_vtmpy_WubRb64" => Intrinsic {
2823             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS },
2824             output: &::I16x64,
2825             definition: Named("llvm.hexagon.V6.vtmpybus")
2826         },
2827         "Wh_vtmpy_WubRb128" => Intrinsic {
2828             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS },
2829             output: &::I16x128,
2830             definition: Named("llvm.hexagon.V6.vtmpybus.128B")
2831         },
2832         "Wh_vtmpyacc_WhWubRb64" => Intrinsic {
2833             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS },
2834             output: &::I16x64,
2835             definition: Named("llvm.hexagon.V6.vtmpybus.acc")
2836         },
2837         "Wh_vtmpyacc_WhWubRb128" => Intrinsic {
2838             inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS },
2839             output: &::I16x128,
2840             definition: Named("llvm.hexagon.V6.vtmpybus.acc.128B")
2841         },
2842         "Ww_vtmpy_WhRb64" => Intrinsic {
2843             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS },
2844             output: &::I32x32,
2845             definition: Named("llvm.hexagon.V6.vtmpyhb")
2846         },
2847         "Ww_vtmpy_WhRb128" => Intrinsic {
2848             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS },
2849             output: &::I32x64,
2850             definition: Named("llvm.hexagon.V6.vtmpyhb.128B")
2851         },
2852         "Wh_vunpack_Vb64" => Intrinsic {
2853             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS },
2854             output: &::I16x64,
2855             definition: Named("llvm.hexagon.V6.vunpackb")
2856         },
2857         "Wuh_vunpack_Vub64" => Intrinsic {
2858             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x64]; &INPUTS },
2859             output: &::U16x64,
2860             definition: Named("llvm.hexagon.V6.vunpackub")
2861         },
2862         "Ww_vunpack_Vh64" => Intrinsic {
2863             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS },
2864             output: &::I32x32,
2865             definition: Named("llvm.hexagon.V6.vunpackh")
2866         },
2867         "Wuw_vunpack_Vuh64" => Intrinsic {
2868             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS },
2869             output: &::U32x32,
2870             definition: Named("llvm.hexagon.V6.vunpackuh")
2871         },
2872         "Wh_vunpack_Vb128" => Intrinsic {
2873             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS },
2874             output: &::I16x128,
2875             definition: Named("llvm.hexagon.V6.vunpackb.128B")
2876         },
2877         "Wuh_vunpack_Vub128" => Intrinsic {
2878             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x128]; &INPUTS },
2879             output: &::U16x128,
2880             definition: Named("llvm.hexagon.V6.vunpackub.128B")
2881         },
2882         "Ww_vunpack_Vh128" => Intrinsic {
2883             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS },
2884             output: &::I32x64,
2885             definition: Named("llvm.hexagon.V6.vunpackh.128B")
2886         },
2887         "Wuw_vunpack_Vuh128" => Intrinsic {
2888             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS },
2889             output: &::U32x64,
2890             definition: Named("llvm.hexagon.V6.vunpackuh.128B")
2891         },
2892         "Wh_vunpackoor_WhVb64" => Intrinsic {
2893             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I8x64]; &INPUTS },
2894             output: &::I16x64,
2895             definition: Named("llvm.hexagon.V6.vunpackob")
2896         },
2897         "Ww_vunpackoor_WwVh64" => Intrinsic {
2898             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x32]; &INPUTS },
2899             output: &::I32x32,
2900             definition: Named("llvm.hexagon.V6.vunpackoh")
2901         },
2902         "Wh_vunpackoor_WhVb128" => Intrinsic {
2903             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I8x128]; &INPUTS },
2904             output: &::I16x128,
2905             definition: Named("llvm.hexagon.V6.vunpackob.128B")
2906         },
2907         "Ww_vunpackoor_WwVh128" => Intrinsic {
2908             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I16x64]; &INPUTS },
2909             output: &::I32x64,
2910             definition: Named("llvm.hexagon.V6.vunpackoh.128B")
2911         },
2912         "Ww_vtmpyacc_WwWhRb64" => Intrinsic {
2913             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS },
2914             output: &::I32x32,
2915             definition: Named("llvm.hexagon.V6.vtmpyhb.acc")
2916         },
2917         "Ww_vtmpyacc_WwWhRb128" => Intrinsic {
2918             inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS },
2919             output: &::I32x64,
2920             definition: Named("llvm.hexagon.V6.vtmpyhb.acc.128B")
2921         },
2922         "V_vxor_VV64" => Intrinsic {
2923             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS },
2924             output: &::U16x32,
2925             definition: Named("llvm.hexagon.V6.vxor")
2926         },
2927         "V_vxor_VV128" => Intrinsic {
2928             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS },
2929             output: &::U16x64,
2930             definition: Named("llvm.hexagon.V6.vxor.128B")
2931         },
2932         _ => return None,
2933     })
2934 }