src/librustc_platform_intrinsics/arm.rs

   1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
   2 // file at the top-level directory of this distribution and at
   3 // http://rust-lang.org/COPYRIGHT.
   4 //
   5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
   6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
   7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
   8 // option. This file may not be copied, modified, or distributed
   9 // except according to those terms.
  10
  11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
  12 // ignore-tidy-linelength
  13
  14 #![allow(unused_imports)]
  15
  16 use {Intrinsic, Type};
  17 use IntrinsicDef::Named;
  18 use rustc::middle::ty::TyCtxt;
  19
  20 // The default inlining settings trigger a pathological behaviour in
  21 // LLVM, which causes makes compilation very slow. See #28273.
  22 #[inline(never)]
  23 pub fn find<'tcx>(_tcx: &TyCtxt<'tcx>, name: &str) -> Option<Intrinsic> {
  24     if !name.starts_with("arm_v") { return None }
  25     Some(match &name["arm_v".len()..] {
  26         "hadd_s8" => Intrinsic {
  27             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  28             output: &::I8x8,
  29             definition: Named("llvm.neon.vhadds.v8i8")
  30         },
  31         "hadd_u8" => Intrinsic {
  32             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  33             output: &::U8x8,
  34             definition: Named("llvm.neon.vhaddu.v8i8")
  35         },
  36         "hadd_s16" => Intrinsic {
  37             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  38             output: &::I16x4,
  39             definition: Named("llvm.neon.vhadds.v4i16")
  40         },
  41         "hadd_u16" => Intrinsic {
  42             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
  43             output: &::U16x4,
  44             definition: Named("llvm.neon.vhaddu.v4i16")
  45         },
  46         "hadd_s32" => Intrinsic {
  47             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
  48             output: &::I32x2,
  49             definition: Named("llvm.neon.vhadds.v2i32")
  50         },
  51         "hadd_u32" => Intrinsic {
  52             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  53             output: &::U32x2,
  54             definition: Named("llvm.neon.vhaddu.v2i32")
  55         },
  56         "haddq_s8" => Intrinsic {
  57             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
  58             output: &::I8x16,
  59             definition: Named("llvm.neon.vhadds.v16i8")
  60         },
  61         "haddq_u8" => Intrinsic {
  62             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
  63             output: &::U8x16,
  64             definition: Named("llvm.neon.vhaddu.v16i8")
  65         },
  66         "haddq_s16" => Intrinsic {
  67             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
  68             output: &::I16x8,
  69             definition: Named("llvm.neon.vhadds.v8i16")
  70         },
  71         "haddq_u16" => Intrinsic {
  72             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
  73             output: &::U16x8,
  74             definition: Named("llvm.neon.vhaddu.v8i16")
  75         },
  76         "haddq_s32" => Intrinsic {
  77             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
  78             output: &::I32x4,
  79             definition: Named("llvm.neon.vhadds.v4i32")
  80         },
  81         "haddq_u32" => Intrinsic {
  82             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  83             output: &::U32x4,
  84             definition: Named("llvm.neon.vhaddu.v4i32")
  85         },
  86         "rhadd_s8" => Intrinsic {
  87             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  88             output: &::I8x8,
  89             definition: Named("llvm.neon.vrhadds.v8i8")
  90         },
  91         "rhadd_u8" => Intrinsic {
  92             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  93             output: &::U8x8,
  94             definition: Named("llvm.neon.vrhaddu.v8i8")
  95         },
  96         "rhadd_s16" => Intrinsic {
  97             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  98             output: &::I16x4,
  99             definition: Named("llvm.neon.vrhadds.v4i16")
 100         },
 101         "rhadd_u16" => Intrinsic {
 102             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 103             output: &::U16x4,
 104             definition: Named("llvm.neon.vrhaddu.v4i16")
 105         },
 106         "rhadd_s32" => Intrinsic {
 107             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 108             output: &::I32x2,
 109             definition: Named("llvm.neon.vrhadds.v2i32")
 110         },
 111         "rhadd_u32" => Intrinsic {
 112             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 113             output: &::U32x2,
 114             definition: Named("llvm.neon.vrhaddu.v2i32")
 115         },
 116         "rhaddq_s8" => Intrinsic {
 117             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 118             output: &::I8x16,
 119             definition: Named("llvm.neon.vrhadds.v16i8")
 120         },
 121         "rhaddq_u8" => Intrinsic {
 122             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 123             output: &::U8x16,
 124             definition: Named("llvm.neon.vrhaddu.v16i8")
 125         },
 126         "rhaddq_s16" => Intrinsic {
 127             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 128             output: &::I16x8,
 129             definition: Named("llvm.neon.vrhadds.v8i16")
 130         },
 131         "rhaddq_u16" => Intrinsic {
 132             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 133             output: &::U16x8,
 134             definition: Named("llvm.neon.vrhaddu.v8i16")
 135         },
 136         "rhaddq_s32" => Intrinsic {
 137             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 138             output: &::I32x4,
 139             definition: Named("llvm.neon.vrhadds.v4i32")
 140         },
 141         "rhaddq_u32" => Intrinsic {
 142             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 143             output: &::U32x4,
 144             definition: Named("llvm.neon.vrhaddu.v4i32")
 145         },
 146         "qadd_s8" => Intrinsic {
 147             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 148             output: &::I8x8,
 149             definition: Named("llvm.neon.vqadds.v8i8")
 150         },
 151         "qadd_u8" => Intrinsic {
 152             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 153             output: &::U8x8,
 154             definition: Named("llvm.neon.vqaddu.v8i8")
 155         },
 156         "qadd_s16" => Intrinsic {
 157             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 158             output: &::I16x4,
 159             definition: Named("llvm.neon.vqadds.v4i16")
 160         },
 161         "qadd_u16" => Intrinsic {
 162             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 163             output: &::U16x4,
 164             definition: Named("llvm.neon.vqaddu.v4i16")
 165         },
 166         "qadd_s32" => Intrinsic {
 167             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 168             output: &::I32x2,
 169             definition: Named("llvm.neon.vqadds.v2i32")
 170         },
 171         "qadd_u32" => Intrinsic {
 172             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 173             output: &::U32x2,
 174             definition: Named("llvm.neon.vqaddu.v2i32")
 175         },
 176         "qadd_s64" => Intrinsic {
 177             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 178             output: &::I64x1,
 179             definition: Named("llvm.neon.vqadds.v1i64")
 180         },
 181         "qadd_u64" => Intrinsic {
 182             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 183             output: &::U64x1,
 184             definition: Named("llvm.neon.vqaddu.v1i64")
 185         },
 186         "qaddq_s8" => Intrinsic {
 187             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 188             output: &::I8x16,
 189             definition: Named("llvm.neon.vqadds.v16i8")
 190         },
 191         "qaddq_u8" => Intrinsic {
 192             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 193             output: &::U8x16,
 194             definition: Named("llvm.neon.vqaddu.v16i8")
 195         },
 196         "qaddq_s16" => Intrinsic {
 197             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 198             output: &::I16x8,
 199             definition: Named("llvm.neon.vqadds.v8i16")
 200         },
 201         "qaddq_u16" => Intrinsic {
 202             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 203             output: &::U16x8,
 204             definition: Named("llvm.neon.vqaddu.v8i16")
 205         },
 206         "qaddq_s32" => Intrinsic {
 207             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 208             output: &::I32x4,
 209             definition: Named("llvm.neon.vqadds.v4i32")
 210         },
 211         "qaddq_u32" => Intrinsic {
 212             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 213             output: &::U32x4,
 214             definition: Named("llvm.neon.vqaddu.v4i32")
 215         },
 216         "qaddq_s64" => Intrinsic {
 217             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 218             output: &::I64x2,
 219             definition: Named("llvm.neon.vqadds.v2i64")
 220         },
 221         "qaddq_u64" => Intrinsic {
 222             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 223             output: &::U64x2,
 224             definition: Named("llvm.neon.vqaddu.v2i64")
 225         },
 226         "raddhn_s16" => Intrinsic {
 227             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 228             output: &::I8x8,
 229             definition: Named("llvm.neon.vraddhn.v8i8")
 230         },
 231         "raddhn_u16" => Intrinsic {
 232             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 233             output: &::U8x8,
 234             definition: Named("llvm.neon.vraddhn.v8i8")
 235         },
 236         "raddhn_s32" => Intrinsic {
 237             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 238             output: &::I16x4,
 239             definition: Named("llvm.neon.vraddhn.v4i16")
 240         },
 241         "raddhn_u32" => Intrinsic {
 242             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 243             output: &::U16x4,
 244             definition: Named("llvm.neon.vraddhn.v4i16")
 245         },
 246         "raddhn_s64" => Intrinsic {
 247             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 248             output: &::I32x2,
 249             definition: Named("llvm.neon.vraddhn.v2i32")
 250         },
 251         "raddhn_u64" => Intrinsic {
 252             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 253             output: &::U32x2,
 254             definition: Named("llvm.neon.vraddhn.v2i32")
 255         },
 256         "fma_f32" => Intrinsic {
 257             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 258             output: &::F32x2,
 259             definition: Named("llvm.fma.v2f32")
 260         },
 261         "fmaq_f32" => Intrinsic {
 262             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 263             output: &::F32x4,
 264             definition: Named("llvm.fma.v4f32")
 265         },
 266         "qdmulh_s16" => Intrinsic {
 267             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 268             output: &::I16x4,
 269             definition: Named("llvm.neon.vsqdmulh.v4i16")
 270         },
 271         "qdmulh_s32" => Intrinsic {
 272             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 273             output: &::I32x2,
 274             definition: Named("llvm.neon.vsqdmulh.v2i32")
 275         },
 276         "qdmulhq_s16" => Intrinsic {
 277             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 278             output: &::I16x8,
 279             definition: Named("llvm.neon.vsqdmulh.v8i16")
 280         },
 281         "qdmulhq_s32" => Intrinsic {
 282             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 283             output: &::I32x4,
 284             definition: Named("llvm.neon.vsqdmulh.v4i32")
 285         },
 286         "qrdmulh_s16" => Intrinsic {
 287             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 288             output: &::I16x4,
 289             definition: Named("llvm.neon.vsqrdmulh.v4i16")
 290         },
 291         "qrdmulh_s32" => Intrinsic {
 292             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 293             output: &::I32x2,
 294             definition: Named("llvm.neon.vsqrdmulh.v2i32")
 295         },
 296         "qrdmulhq_s16" => Intrinsic {
 297             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 298             output: &::I16x8,
 299             definition: Named("llvm.neon.vsqrdmulh.v8i16")
 300         },
 301         "qrdmulhq_s32" => Intrinsic {
 302             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 303             output: &::I32x4,
 304             definition: Named("llvm.neon.vsqrdmulh.v4i32")
 305         },
 306         "mull_s8" => Intrinsic {
 307             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 308             output: &::I16x8,
 309             definition: Named("llvm.neon.vmulls.v8i16")
 310         },
 311         "mull_u8" => Intrinsic {
 312             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 313             output: &::U16x8,
 314             definition: Named("llvm.neon.vmullu.v8i16")
 315         },
 316         "mull_s16" => Intrinsic {
 317             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 318             output: &::I32x4,
 319             definition: Named("llvm.neon.vmulls.v4i32")
 320         },
 321         "mull_u16" => Intrinsic {
 322             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 323             output: &::U32x4,
 324             definition: Named("llvm.neon.vmullu.v4i32")
 325         },
 326         "mull_s32" => Intrinsic {
 327             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 328             output: &::I64x2,
 329             definition: Named("llvm.neon.vmulls.v2i64")
 330         },
 331         "mull_u32" => Intrinsic {
 332             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 333             output: &::U64x2,
 334             definition: Named("llvm.neon.vmullu.v2i64")
 335         },
 336         "qdmullq_s8" => Intrinsic {
 337             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 338             output: &::I16x8,
 339             definition: Named("llvm.neon.vsqdmull.v8i16")
 340         },
 341         "qdmullq_s16" => Intrinsic {
 342             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 343             output: &::I32x4,
 344             definition: Named("llvm.neon.vsqdmull.v4i32")
 345         },
 346         "hsub_s8" => Intrinsic {
 347             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 348             output: &::I8x8,
 349             definition: Named("llvm.neon.vhsubs.v8i8")
 350         },
 351         "hsub_u8" => Intrinsic {
 352             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 353             output: &::U8x8,
 354             definition: Named("llvm.neon.vhsubu.v8i8")
 355         },
 356         "hsub_s16" => Intrinsic {
 357             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 358             output: &::I16x4,
 359             definition: Named("llvm.neon.vhsubs.v4i16")
 360         },
 361         "hsub_u16" => Intrinsic {
 362             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 363             output: &::U16x4,
 364             definition: Named("llvm.neon.vhsubu.v4i16")
 365         },
 366         "hsub_s32" => Intrinsic {
 367             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 368             output: &::I32x2,
 369             definition: Named("llvm.neon.vhsubs.v2i32")
 370         },
 371         "hsub_u32" => Intrinsic {
 372             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 373             output: &::U32x2,
 374             definition: Named("llvm.neon.vhsubu.v2i32")
 375         },
 376         "hsubq_s8" => Intrinsic {
 377             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 378             output: &::I8x16,
 379             definition: Named("llvm.neon.vhsubs.v16i8")
 380         },
 381         "hsubq_u8" => Intrinsic {
 382             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 383             output: &::U8x16,
 384             definition: Named("llvm.neon.vhsubu.v16i8")
 385         },
 386         "hsubq_s16" => Intrinsic {
 387             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 388             output: &::I16x8,
 389             definition: Named("llvm.neon.vhsubs.v8i16")
 390         },
 391         "hsubq_u16" => Intrinsic {
 392             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 393             output: &::U16x8,
 394             definition: Named("llvm.neon.vhsubu.v8i16")
 395         },
 396         "hsubq_s32" => Intrinsic {
 397             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 398             output: &::I32x4,
 399             definition: Named("llvm.neon.vhsubs.v4i32")
 400         },
 401         "hsubq_u32" => Intrinsic {
 402             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 403             output: &::U32x4,
 404             definition: Named("llvm.neon.vhsubu.v4i32")
 405         },
 406         "qsub_s8" => Intrinsic {
 407             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 408             output: &::I8x8,
 409             definition: Named("llvm.neon.vqsubs.v8i8")
 410         },
 411         "qsub_u8" => Intrinsic {
 412             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 413             output: &::U8x8,
 414             definition: Named("llvm.neon.vqsubu.v8i8")
 415         },
 416         "qsub_s16" => Intrinsic {
 417             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 418             output: &::I16x4,
 419             definition: Named("llvm.neon.vqsubs.v4i16")
 420         },
 421         "qsub_u16" => Intrinsic {
 422             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 423             output: &::U16x4,
 424             definition: Named("llvm.neon.vqsubu.v4i16")
 425         },
 426         "qsub_s32" => Intrinsic {
 427             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 428             output: &::I32x2,
 429             definition: Named("llvm.neon.vqsubs.v2i32")
 430         },
 431         "qsub_u32" => Intrinsic {
 432             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 433             output: &::U32x2,
 434             definition: Named("llvm.neon.vqsubu.v2i32")
 435         },
 436         "qsub_s64" => Intrinsic {
 437             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 438             output: &::I64x1,
 439             definition: Named("llvm.neon.vqsubs.v1i64")
 440         },
 441         "qsub_u64" => Intrinsic {
 442             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 443             output: &::U64x1,
 444             definition: Named("llvm.neon.vqsubu.v1i64")
 445         },
 446         "qsubq_s8" => Intrinsic {
 447             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 448             output: &::I8x16,
 449             definition: Named("llvm.neon.vqsubs.v16i8")
 450         },
 451         "qsubq_u8" => Intrinsic {
 452             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 453             output: &::U8x16,
 454             definition: Named("llvm.neon.vqsubu.v16i8")
 455         },
 456         "qsubq_s16" => Intrinsic {
 457             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 458             output: &::I16x8,
 459             definition: Named("llvm.neon.vqsubs.v8i16")
 460         },
 461         "qsubq_u16" => Intrinsic {
 462             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 463             output: &::U16x8,
 464             definition: Named("llvm.neon.vqsubu.v8i16")
 465         },
 466         "qsubq_s32" => Intrinsic {
 467             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 468             output: &::I32x4,
 469             definition: Named("llvm.neon.vqsubs.v4i32")
 470         },
 471         "qsubq_u32" => Intrinsic {
 472             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 473             output: &::U32x4,
 474             definition: Named("llvm.neon.vqsubu.v4i32")
 475         },
 476         "qsubq_s64" => Intrinsic {
 477             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 478             output: &::I64x2,
 479             definition: Named("llvm.neon.vqsubs.v2i64")
 480         },
 481         "qsubq_u64" => Intrinsic {
 482             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 483             output: &::U64x2,
 484             definition: Named("llvm.neon.vqsubu.v2i64")
 485         },
 486         "rsubhn_s16" => Intrinsic {
 487             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 488             output: &::I8x8,
 489             definition: Named("llvm.neon.vrsubhn.v8i8")
 490         },
 491         "rsubhn_u16" => Intrinsic {
 492             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 493             output: &::U8x8,
 494             definition: Named("llvm.neon.vrsubhn.v8i8")
 495         },
 496         "rsubhn_s32" => Intrinsic {
 497             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 498             output: &::I16x4,
 499             definition: Named("llvm.neon.vrsubhn.v4i16")
 500         },
 501         "rsubhn_u32" => Intrinsic {
 502             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 503             output: &::U16x4,
 504             definition: Named("llvm.neon.vrsubhn.v4i16")
 505         },
 506         "rsubhn_s64" => Intrinsic {
 507             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 508             output: &::I32x2,
 509             definition: Named("llvm.neon.vrsubhn.v2i32")
 510         },
 511         "rsubhn_u64" => Intrinsic {
 512             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 513             output: &::U32x2,
 514             definition: Named("llvm.neon.vrsubhn.v2i32")
 515         },
 516         "abd_s8" => Intrinsic {
 517             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 518             output: &::I8x8,
 519             definition: Named("llvm.neon.vabds.v8i8")
 520         },
 521         "abd_u8" => Intrinsic {
 522             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 523             output: &::U8x8,
 524             definition: Named("llvm.neon.vabdu.v8i8")
 525         },
 526         "abd_s16" => Intrinsic {
 527             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 528             output: &::I16x4,
 529             definition: Named("llvm.neon.vabds.v4i16")
 530         },
 531         "abd_u16" => Intrinsic {
 532             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 533             output: &::U16x4,
 534             definition: Named("llvm.neon.vabdu.v4i16")
 535         },
 536         "abd_s32" => Intrinsic {
 537             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 538             output: &::I32x2,
 539             definition: Named("llvm.neon.vabds.v2i32")
 540         },
 541         "abd_u32" => Intrinsic {
 542             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 543             output: &::U32x2,
 544             definition: Named("llvm.neon.vabdu.v2i32")
 545         },
 546         "abd_f32" => Intrinsic {
 547             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 548             output: &::F32x2,
 549             definition: Named("llvm.neon.vabdf.v2f32")
 550         },
 551         "abdq_s8" => Intrinsic {
 552             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 553             output: &::I8x16,
 554             definition: Named("llvm.neon.vabds.v16i8")
 555         },
 556         "abdq_u8" => Intrinsic {
 557             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 558             output: &::U8x16,
 559             definition: Named("llvm.neon.vabdu.v16i8")
 560         },
 561         "abdq_s16" => Intrinsic {
 562             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 563             output: &::I16x8,
 564             definition: Named("llvm.neon.vabds.v8i16")
 565         },
 566         "abdq_u16" => Intrinsic {
 567             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 568             output: &::U16x8,
 569             definition: Named("llvm.neon.vabdu.v8i16")
 570         },
 571         "abdq_s32" => Intrinsic {
 572             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 573             output: &::I32x4,
 574             definition: Named("llvm.neon.vabds.v4i32")
 575         },
 576         "abdq_u32" => Intrinsic {
 577             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 578             output: &::U32x4,
 579             definition: Named("llvm.neon.vabdu.v4i32")
 580         },
 581         "abdq_f32" => Intrinsic {
 582             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 583             output: &::F32x4,
 584             definition: Named("llvm.neon.vabdf.v4f32")
 585         },
 586         "max_s8" => Intrinsic {
 587             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 588             output: &::I8x8,
 589             definition: Named("llvm.neon.vmaxs.v8i8")
 590         },
 591         "max_u8" => Intrinsic {
 592             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 593             output: &::U8x8,
 594             definition: Named("llvm.neon.vmaxu.v8i8")
 595         },
 596         "max_s16" => Intrinsic {
 597             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 598             output: &::I16x4,
 599             definition: Named("llvm.neon.vmaxs.v4i16")
 600         },
 601         "max_u16" => Intrinsic {
 602             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 603             output: &::U16x4,
 604             definition: Named("llvm.neon.vmaxu.v4i16")
 605         },
 606         "max_s32" => Intrinsic {
 607             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 608             output: &::I32x2,
 609             definition: Named("llvm.neon.vmaxs.v2i32")
 610         },
 611         "max_u32" => Intrinsic {
 612             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 613             output: &::U32x2,
 614             definition: Named("llvm.neon.vmaxu.v2i32")
 615         },
 616         "max_f32" => Intrinsic {
 617             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 618             output: &::F32x2,
 619             definition: Named("llvm.neon.vmaxf.v2f32")
 620         },
 621         "maxq_s8" => Intrinsic {
 622             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 623             output: &::I8x16,
 624             definition: Named("llvm.neon.vmaxs.v16i8")
 625         },
 626         "maxq_u8" => Intrinsic {
 627             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 628             output: &::U8x16,
 629             definition: Named("llvm.neon.vmaxu.v16i8")
 630         },
 631         "maxq_s16" => Intrinsic {
 632             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 633             output: &::I16x8,
 634             definition: Named("llvm.neon.vmaxs.v8i16")
 635         },
 636         "maxq_u16" => Intrinsic {
 637             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 638             output: &::U16x8,
 639             definition: Named("llvm.neon.vmaxu.v8i16")
 640         },
 641         "maxq_s32" => Intrinsic {
 642             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 643             output: &::I32x4,
 644             definition: Named("llvm.neon.vmaxs.v4i32")
 645         },
 646         "maxq_u32" => Intrinsic {
 647             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 648             output: &::U32x4,
 649             definition: Named("llvm.neon.vmaxu.v4i32")
 650         },
 651         "maxq_f32" => Intrinsic {
 652             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 653             output: &::F32x4,
 654             definition: Named("llvm.neon.vmaxf.v4f32")
 655         },
 656         "min_s8" => Intrinsic {
 657             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 658             output: &::I8x8,
 659             definition: Named("llvm.neon.vmins.v8i8")
 660         },
 661         "min_u8" => Intrinsic {
 662             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 663             output: &::U8x8,
 664             definition: Named("llvm.neon.vminu.v8i8")
 665         },
 666         "min_s16" => Intrinsic {
 667             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 668             output: &::I16x4,
 669             definition: Named("llvm.neon.vmins.v4i16")
 670         },
 671         "min_u16" => Intrinsic {
 672             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 673             output: &::U16x4,
 674             definition: Named("llvm.neon.vminu.v4i16")
 675         },
 676         "min_s32" => Intrinsic {
 677             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 678             output: &::I32x2,
 679             definition: Named("llvm.neon.vmins.v2i32")
 680         },
 681         "min_u32" => Intrinsic {
 682             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 683             output: &::U32x2,
 684             definition: Named("llvm.neon.vminu.v2i32")
 685         },
 686         "min_f32" => Intrinsic {
 687             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 688             output: &::F32x2,
 689             definition: Named("llvm.neon.vminf.v2f32")
 690         },
 691         "minq_s8" => Intrinsic {
 692             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 693             output: &::I8x16,
 694             definition: Named("llvm.neon.vmins.v16i8")
 695         },
 696         "minq_u8" => Intrinsic {
 697             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 698             output: &::U8x16,
 699             definition: Named("llvm.neon.vminu.v16i8")
 700         },
 701         "minq_s16" => Intrinsic {
 702             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 703             output: &::I16x8,
 704             definition: Named("llvm.neon.vmins.v8i16")
 705         },
 706         "minq_u16" => Intrinsic {
 707             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 708             output: &::U16x8,
 709             definition: Named("llvm.neon.vminu.v8i16")
 710         },
 711         "minq_s32" => Intrinsic {
 712             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 713             output: &::I32x4,
 714             definition: Named("llvm.neon.vmins.v4i32")
 715         },
 716         "minq_u32" => Intrinsic {
 717             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 718             output: &::U32x4,
 719             definition: Named("llvm.neon.vminu.v4i32")
 720         },
 721         "minq_f32" => Intrinsic {
 722             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 723             output: &::F32x4,
 724             definition: Named("llvm.neon.vminf.v4f32")
 725         },
 726         "shl_s8" => Intrinsic {
 727             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 728             output: &::I8x8,
 729             definition: Named("llvm.neon.vshls.v8i8")
 730         },
 731         "shl_u8" => Intrinsic {
 732             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 733             output: &::U8x8,
 734             definition: Named("llvm.neon.vshlu.v8i8")
 735         },
 736         "shl_s16" => Intrinsic {
 737             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 738             output: &::I16x4,
 739             definition: Named("llvm.neon.vshls.v4i16")
 740         },
 741         "shl_u16" => Intrinsic {
 742             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 743             output: &::U16x4,
 744             definition: Named("llvm.neon.vshlu.v4i16")
 745         },
 746         "shl_s32" => Intrinsic {
 747             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 748             output: &::I32x2,
 749             definition: Named("llvm.neon.vshls.v2i32")
 750         },
 751         "shl_u32" => Intrinsic {
 752             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 753             output: &::U32x2,
 754             definition: Named("llvm.neon.vshlu.v2i32")
 755         },
 756         "shl_s64" => Intrinsic {
 757             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 758             output: &::I64x1,
 759             definition: Named("llvm.neon.vshls.v1i64")
 760         },
 761         "shl_u64" => Intrinsic {
 762             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 763             output: &::U64x1,
 764             definition: Named("llvm.neon.vshlu.v1i64")
 765         },
 766         "shlq_s8" => Intrinsic {
 767             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 768             output: &::I8x16,
 769             definition: Named("llvm.neon.vshls.v16i8")
 770         },
 771         "shlq_u8" => Intrinsic {
 772             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 773             output: &::U8x16,
 774             definition: Named("llvm.neon.vshlu.v16i8")
 775         },
 776         "shlq_s16" => Intrinsic {
 777             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 778             output: &::I16x8,
 779             definition: Named("llvm.neon.vshls.v8i16")
 780         },
 781         "shlq_u16" => Intrinsic {
 782             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 783             output: &::U16x8,
 784             definition: Named("llvm.neon.vshlu.v8i16")
 785         },
 786         "shlq_s32" => Intrinsic {
 787             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 788             output: &::I32x4,
 789             definition: Named("llvm.neon.vshls.v4i32")
 790         },
 791         "shlq_u32" => Intrinsic {
 792             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 793             output: &::U32x4,
 794             definition: Named("llvm.neon.vshlu.v4i32")
 795         },
 796         "shlq_s64" => Intrinsic {
 797             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 798             output: &::I64x2,
 799             definition: Named("llvm.neon.vshls.v2i64")
 800         },
 801         "shlq_u64" => Intrinsic {
 802             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 803             output: &::U64x2,
 804             definition: Named("llvm.neon.vshlu.v2i64")
 805         },
 806         "qshl_s8" => Intrinsic {
 807             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 808             output: &::I8x8,
 809             definition: Named("llvm.neon.vqshls.v8i8")
 810         },
 811         "qshl_u8" => Intrinsic {
 812             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 813             output: &::U8x8,
 814             definition: Named("llvm.neon.vqshlu.v8i8")
 815         },
 816         "qshl_s16" => Intrinsic {
 817             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 818             output: &::I16x4,
 819             definition: Named("llvm.neon.vqshls.v4i16")
 820         },
 821         "qshl_u16" => Intrinsic {
 822             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 823             output: &::U16x4,
 824             definition: Named("llvm.neon.vqshlu.v4i16")
 825         },
 826         "qshl_s32" => Intrinsic {
 827             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 828             output: &::I32x2,
 829             definition: Named("llvm.neon.vqshls.v2i32")
 830         },
 831         "qshl_u32" => Intrinsic {
 832             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 833             output: &::U32x2,
 834             definition: Named("llvm.neon.vqshlu.v2i32")
 835         },
 836         "qshl_s64" => Intrinsic {
 837             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 838             output: &::I64x1,
 839             definition: Named("llvm.neon.vqshls.v1i64")
 840         },
 841         "qshl_u64" => Intrinsic {
 842             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 843             output: &::U64x1,
 844             definition: Named("llvm.neon.vqshlu.v1i64")
 845         },
 846         "qshlq_s8" => Intrinsic {
 847             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 848             output: &::I8x16,
 849             definition: Named("llvm.neon.vqshls.v16i8")
 850         },
 851         "qshlq_u8" => Intrinsic {
 852             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 853             output: &::U8x16,
 854             definition: Named("llvm.neon.vqshlu.v16i8")
 855         },
 856         "qshlq_s16" => Intrinsic {
 857             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 858             output: &::I16x8,
 859             definition: Named("llvm.neon.vqshls.v8i16")
 860         },
 861         "qshlq_u16" => Intrinsic {
 862             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 863             output: &::U16x8,
 864             definition: Named("llvm.neon.vqshlu.v8i16")
 865         },
 866         "qshlq_s32" => Intrinsic {
 867             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 868             output: &::I32x4,
 869             definition: Named("llvm.neon.vqshls.v4i32")
 870         },
 871         "qshlq_u32" => Intrinsic {
 872             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 873             output: &::U32x4,
 874             definition: Named("llvm.neon.vqshlu.v4i32")
 875         },
 876         "qshlq_s64" => Intrinsic {
 877             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 878             output: &::I64x2,
 879             definition: Named("llvm.neon.vqshls.v2i64")
 880         },
 881         "qshlq_u64" => Intrinsic {
 882             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 883             output: &::U64x2,
 884             definition: Named("llvm.neon.vqshlu.v2i64")
 885         },
 886         "rshl_s8" => Intrinsic {
 887             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 888             output: &::I8x8,
 889             definition: Named("llvm.neon.vrshls.v8i8")
 890         },
 891         "rshl_u8" => Intrinsic {
 892             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 893             output: &::U8x8,
 894             definition: Named("llvm.neon.vrshlu.v8i8")
 895         },
 896         "rshl_s16" => Intrinsic {
 897             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 898             output: &::I16x4,
 899             definition: Named("llvm.neon.vrshls.v4i16")
 900         },
 901         "rshl_u16" => Intrinsic {
 902             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 903             output: &::U16x4,
 904             definition: Named("llvm.neon.vrshlu.v4i16")
 905         },
 906         "rshl_s32" => Intrinsic {
 907             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 908             output: &::I32x2,
 909             definition: Named("llvm.neon.vrshls.v2i32")
 910         },
 911         "rshl_u32" => Intrinsic {
 912             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 913             output: &::U32x2,
 914             definition: Named("llvm.neon.vrshlu.v2i32")
 915         },
 916         "rshl_s64" => Intrinsic {
 917             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 918             output: &::I64x1,
 919             definition: Named("llvm.neon.vrshls.v1i64")
 920         },
 921         "rshl_u64" => Intrinsic {
 922             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 923             output: &::U64x1,
 924             definition: Named("llvm.neon.vrshlu.v1i64")
 925         },
 926         "rshlq_s8" => Intrinsic {
 927             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 928             output: &::I8x16,
 929             definition: Named("llvm.neon.vrshls.v16i8")
 930         },
 931         "rshlq_u8" => Intrinsic {
 932             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 933             output: &::U8x16,
 934             definition: Named("llvm.neon.vrshlu.v16i8")
 935         },
 936         "rshlq_s16" => Intrinsic {
 937             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 938             output: &::I16x8,
 939             definition: Named("llvm.neon.vrshls.v8i16")
 940         },
 941         "rshlq_u16" => Intrinsic {
 942             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 943             output: &::U16x8,
 944             definition: Named("llvm.neon.vrshlu.v8i16")
 945         },
 946         "rshlq_s32" => Intrinsic {
 947             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 948             output: &::I32x4,
 949             definition: Named("llvm.neon.vrshls.v4i32")
 950         },
 951         "rshlq_u32" => Intrinsic {
 952             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 953             output: &::U32x4,
 954             definition: Named("llvm.neon.vrshlu.v4i32")
 955         },
 956         "rshlq_s64" => Intrinsic {
 957             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 958             output: &::I64x2,
 959             definition: Named("llvm.neon.vrshls.v2i64")
 960         },
 961         "rshlq_u64" => Intrinsic {
 962             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 963             output: &::U64x2,
 964             definition: Named("llvm.neon.vrshlu.v2i64")
 965         },
 966         "qrshl_s8" => Intrinsic {
 967             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 968             output: &::I8x8,
 969             definition: Named("llvm.neon.vqrshls.v8i8")
 970         },
 971         "qrshl_u8" => Intrinsic {
 972             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 973             output: &::U8x8,
 974             definition: Named("llvm.neon.vqrshlu.v8i8")
 975         },
 976         "qrshl_s16" => Intrinsic {
 977             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 978             output: &::I16x4,
 979             definition: Named("llvm.neon.vqrshls.v4i16")
 980         },
 981         "qrshl_u16" => Intrinsic {
 982             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 983             output: &::U16x4,
 984             definition: Named("llvm.neon.vqrshlu.v4i16")
 985         },
 986         "qrshl_s32" => Intrinsic {
 987             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 988             output: &::I32x2,
 989             definition: Named("llvm.neon.vqrshls.v2i32")
 990         },
 991         "qrshl_u32" => Intrinsic {
 992             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 993             output: &::U32x2,
 994             definition: Named("llvm.neon.vqrshlu.v2i32")
 995         },
 996         "qrshl_s64" => Intrinsic {
 997             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 998             output: &::I64x1,
 999             definition: Named("llvm.neon.vqrshls.v1i64")
1000         },
1001         "qrshl_u64" => Intrinsic {
1002             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1003             output: &::U64x1,
1004             definition: Named("llvm.neon.vqrshlu.v1i64")
1005         },
1006         "qrshlq_s8" => Intrinsic {
1007             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1008             output: &::I8x16,
1009             definition: Named("llvm.neon.vqrshls.v16i8")
1010         },
1011         "qrshlq_u8" => Intrinsic {
1012             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1013             output: &::U8x16,
1014             definition: Named("llvm.neon.vqrshlu.v16i8")
1015         },
1016         "qrshlq_s16" => Intrinsic {
1017             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1018             output: &::I16x8,
1019             definition: Named("llvm.neon.vqrshls.v8i16")
1020         },
1021         "qrshlq_u16" => Intrinsic {
1022             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1023             output: &::U16x8,
1024             definition: Named("llvm.neon.vqrshlu.v8i16")
1025         },
1026         "qrshlq_s32" => Intrinsic {
1027             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1028             output: &::I32x4,
1029             definition: Named("llvm.neon.vqrshls.v4i32")
1030         },
1031         "qrshlq_u32" => Intrinsic {
1032             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1033             output: &::U32x4,
1034             definition: Named("llvm.neon.vqrshlu.v4i32")
1035         },
1036         "qrshlq_s64" => Intrinsic {
1037             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1038             output: &::I64x2,
1039             definition: Named("llvm.neon.vqrshls.v2i64")
1040         },
1041         "qrshlq_u64" => Intrinsic {
1042             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1043             output: &::U64x2,
1044             definition: Named("llvm.neon.vqrshlu.v2i64")
1045         },
1046         "qshrun_n_s16" => Intrinsic {
1047             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1048             output: &::I8x8,
1049             definition: Named("llvm.neon.vsqshrun.v8i8")
1050         },
1051         "qshrun_n_s32" => Intrinsic {
1052             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1053             output: &::I16x4,
1054             definition: Named("llvm.neon.vsqshrun.v4i16")
1055         },
1056         "qshrun_n_s64" => Intrinsic {
1057             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1058             output: &::I32x2,
1059             definition: Named("llvm.neon.vsqshrun.v2i32")
1060         },
1061         "qrshrun_n_s16" => Intrinsic {
1062             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1063             output: &::I8x8,
1064             definition: Named("llvm.neon.vsqrshrun.v8i8")
1065         },
1066         "qrshrun_n_s32" => Intrinsic {
1067             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1068             output: &::I16x4,
1069             definition: Named("llvm.neon.vsqrshrun.v4i16")
1070         },
1071         "qrshrun_n_s64" => Intrinsic {
1072             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1073             output: &::I32x2,
1074             definition: Named("llvm.neon.vsqrshrun.v2i32")
1075         },
1076         "qshrn_n_s16" => Intrinsic {
1077             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1078             output: &::I8x8,
1079             definition: Named("llvm.neon.vqshrns.v8i8")
1080         },
1081         "qshrn_n_u16" => Intrinsic {
1082             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1083             output: &::U8x8,
1084             definition: Named("llvm.neon.vqshrnu.v8i8")
1085         },
1086         "qshrn_n_s32" => Intrinsic {
1087             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1088             output: &::I16x4,
1089             definition: Named("llvm.neon.vqshrns.v4i16")
1090         },
1091         "qshrn_n_u32" => Intrinsic {
1092             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1093             output: &::U16x4,
1094             definition: Named("llvm.neon.vqshrnu.v4i16")
1095         },
1096         "qshrn_n_s64" => Intrinsic {
1097             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1098             output: &::I32x2,
1099             definition: Named("llvm.neon.vqshrns.v2i32")
1100         },
1101         "qshrn_n_u64" => Intrinsic {
1102             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1103             output: &::U32x2,
1104             definition: Named("llvm.neon.vqshrnu.v2i32")
1105         },
1106         "rshrn_n_s16" => Intrinsic {
1107             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1108             output: &::I8x8,
1109             definition: Named("llvm.neon.vrshrn.v8i8")
1110         },
1111         "rshrn_n_u16" => Intrinsic {
1112             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1113             output: &::U8x8,
1114             definition: Named("llvm.neon.vrshrn.v8i8")
1115         },
1116         "rshrn_n_s32" => Intrinsic {
1117             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1118             output: &::I16x4,
1119             definition: Named("llvm.neon.vrshrn.v4i16")
1120         },
1121         "rshrn_n_u32" => Intrinsic {
1122             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1123             output: &::U16x4,
1124             definition: Named("llvm.neon.vrshrn.v4i16")
1125         },
1126         "rshrn_n_s64" => Intrinsic {
1127             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1128             output: &::I32x2,
1129             definition: Named("llvm.neon.vrshrn.v2i32")
1130         },
1131         "rshrn_n_u64" => Intrinsic {
1132             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1133             output: &::U32x2,
1134             definition: Named("llvm.neon.vrshrn.v2i32")
1135         },
1136         "qrshrn_n_s16" => Intrinsic {
1137             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1138             output: &::I8x8,
1139             definition: Named("llvm.neon.vqrshrns.v8i8")
1140         },
1141         "qrshrn_n_u16" => Intrinsic {
1142             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1143             output: &::U8x8,
1144             definition: Named("llvm.neon.vqrshrnu.v8i8")
1145         },
1146         "qrshrn_n_s32" => Intrinsic {
1147             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1148             output: &::I16x4,
1149             definition: Named("llvm.neon.vqrshrns.v4i16")
1150         },
1151         "qrshrn_n_u32" => Intrinsic {
1152             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1153             output: &::U16x4,
1154             definition: Named("llvm.neon.vqrshrnu.v4i16")
1155         },
1156         "qrshrn_n_s64" => Intrinsic {
1157             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1158             output: &::I32x2,
1159             definition: Named("llvm.neon.vqrshrns.v2i32")
1160         },
1161         "qrshrn_n_u64" => Intrinsic {
1162             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1163             output: &::U32x2,
1164             definition: Named("llvm.neon.vqrshrnu.v2i32")
1165         },
1166         "sri_s8" => Intrinsic {
1167             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1168             output: &::I8x8,
1169             definition: Named("llvm.neon.vvsri.v8i8")
1170         },
1171         "sri_u8" => Intrinsic {
1172             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1173             output: &::U8x8,
1174             definition: Named("llvm.neon.vvsri.v8i8")
1175         },
1176         "sri_s16" => Intrinsic {
1177             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1178             output: &::I16x4,
1179             definition: Named("llvm.neon.vvsri.v4i16")
1180         },
1181         "sri_u16" => Intrinsic {
1182             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1183             output: &::U16x4,
1184             definition: Named("llvm.neon.vvsri.v4i16")
1185         },
1186         "sri_s32" => Intrinsic {
1187             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1188             output: &::I32x2,
1189             definition: Named("llvm.neon.vvsri.v2i32")
1190         },
1191         "sri_u32" => Intrinsic {
1192             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1193             output: &::U32x2,
1194             definition: Named("llvm.neon.vvsri.v2i32")
1195         },
1196         "sri_s64" => Intrinsic {
1197             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1198             output: &::I64x1,
1199             definition: Named("llvm.neon.vvsri.v1i64")
1200         },
1201         "sri_u64" => Intrinsic {
1202             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1203             output: &::U64x1,
1204             definition: Named("llvm.neon.vvsri.v1i64")
1205         },
1206         "sriq_s8" => Intrinsic {
1207             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1208             output: &::I8x16,
1209             definition: Named("llvm.neon.vvsri.v16i8")
1210         },
1211         "sriq_u8" => Intrinsic {
1212             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1213             output: &::U8x16,
1214             definition: Named("llvm.neon.vvsri.v16i8")
1215         },
1216         "sriq_s16" => Intrinsic {
1217             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1218             output: &::I16x8,
1219             definition: Named("llvm.neon.vvsri.v8i16")
1220         },
1221         "sriq_u16" => Intrinsic {
1222             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1223             output: &::U16x8,
1224             definition: Named("llvm.neon.vvsri.v8i16")
1225         },
1226         "sriq_s32" => Intrinsic {
1227             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1228             output: &::I32x4,
1229             definition: Named("llvm.neon.vvsri.v4i32")
1230         },
1231         "sriq_u32" => Intrinsic {
1232             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1233             output: &::U32x4,
1234             definition: Named("llvm.neon.vvsri.v4i32")
1235         },
1236         "sriq_s64" => Intrinsic {
1237             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1238             output: &::I64x2,
1239             definition: Named("llvm.neon.vvsri.v2i64")
1240         },
1241         "sriq_u64" => Intrinsic {
1242             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1243             output: &::U64x2,
1244             definition: Named("llvm.neon.vvsri.v2i64")
1245         },
1246         "sli_s8" => Intrinsic {
1247             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1248             output: &::I8x8,
1249             definition: Named("llvm.neon.vvsli.v8i8")
1250         },
1251         "sli_u8" => Intrinsic {
1252             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1253             output: &::U8x8,
1254             definition: Named("llvm.neon.vvsli.v8i8")
1255         },
1256         "sli_s16" => Intrinsic {
1257             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1258             output: &::I16x4,
1259             definition: Named("llvm.neon.vvsli.v4i16")
1260         },
1261         "sli_u16" => Intrinsic {
1262             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1263             output: &::U16x4,
1264             definition: Named("llvm.neon.vvsli.v4i16")
1265         },
1266         "sli_s32" => Intrinsic {
1267             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1268             output: &::I32x2,
1269             definition: Named("llvm.neon.vvsli.v2i32")
1270         },
1271         "sli_u32" => Intrinsic {
1272             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1273             output: &::U32x2,
1274             definition: Named("llvm.neon.vvsli.v2i32")
1275         },
1276         "sli_s64" => Intrinsic {
1277             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1278             output: &::I64x1,
1279             definition: Named("llvm.neon.vvsli.v1i64")
1280         },
1281         "sli_u64" => Intrinsic {
1282             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1283             output: &::U64x1,
1284             definition: Named("llvm.neon.vvsli.v1i64")
1285         },
1286         "sliq_s8" => Intrinsic {
1287             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1288             output: &::I8x16,
1289             definition: Named("llvm.neon.vvsli.v16i8")
1290         },
1291         "sliq_u8" => Intrinsic {
1292             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1293             output: &::U8x16,
1294             definition: Named("llvm.neon.vvsli.v16i8")
1295         },
1296         "sliq_s16" => Intrinsic {
1297             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1298             output: &::I16x8,
1299             definition: Named("llvm.neon.vvsli.v8i16")
1300         },
1301         "sliq_u16" => Intrinsic {
1302             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1303             output: &::U16x8,
1304             definition: Named("llvm.neon.vvsli.v8i16")
1305         },
1306         "sliq_s32" => Intrinsic {
1307             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1308             output: &::I32x4,
1309             definition: Named("llvm.neon.vvsli.v4i32")
1310         },
1311         "sliq_u32" => Intrinsic {
1312             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1313             output: &::U32x4,
1314             definition: Named("llvm.neon.vvsli.v4i32")
1315         },
1316         "sliq_s64" => Intrinsic {
1317             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1318             output: &::I64x2,
1319             definition: Named("llvm.neon.vvsli.v2i64")
1320         },
1321         "sliq_u64" => Intrinsic {
1322             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1323             output: &::U64x2,
1324             definition: Named("llvm.neon.vvsli.v2i64")
1325         },
1326         "vqmovn_s16" => Intrinsic {
1327             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1328             output: &::I8x8,
1329             definition: Named("llvm.neon.vqxtns.v8i8")
1330         },
1331         "vqmovn_u16" => Intrinsic {
1332             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1333             output: &::U8x8,
1334             definition: Named("llvm.neon.vqxtnu.v8i8")
1335         },
1336         "vqmovn_s32" => Intrinsic {
1337             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1338             output: &::I16x4,
1339             definition: Named("llvm.neon.vqxtns.v4i16")
1340         },
1341         "vqmovn_u32" => Intrinsic {
1342             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1343             output: &::U16x4,
1344             definition: Named("llvm.neon.vqxtnu.v4i16")
1345         },
1346         "vqmovn_s64" => Intrinsic {
1347             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1348             output: &::I32x2,
1349             definition: Named("llvm.neon.vqxtns.v2i32")
1350         },
1351         "vqmovn_u64" => Intrinsic {
1352             inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
1353             output: &::U32x2,
1354             definition: Named("llvm.neon.vqxtnu.v2i32")
1355         },
1356         "abs_s8" => Intrinsic {
1357             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1358             output: &::I8x8,
1359             definition: Named("llvm.neon.vabs.v8i8")
1360         },
1361         "abs_s16" => Intrinsic {
1362             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1363             output: &::I16x4,
1364             definition: Named("llvm.neon.vabs.v4i16")
1365         },
1366         "abs_s32" => Intrinsic {
1367             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1368             output: &::I32x2,
1369             definition: Named("llvm.neon.vabs.v2i32")
1370         },
1371         "absq_s8" => Intrinsic {
1372             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1373             output: &::I8x16,
1374             definition: Named("llvm.neon.vabs.v16i8")
1375         },
1376         "absq_s16" => Intrinsic {
1377             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1378             output: &::I16x8,
1379             definition: Named("llvm.neon.vabs.v8i16")
1380         },
1381         "absq_s32" => Intrinsic {
1382             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1383             output: &::I32x4,
1384             definition: Named("llvm.neon.vabs.v4i32")
1385         },
1386         "abs_f32" => Intrinsic {
1387             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1388             output: &::F32x2,
1389             definition: Named("llvm.fabs.v2f32")
1390         },
1391         "absq_f32" => Intrinsic {
1392             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1393             output: &::F32x4,
1394             definition: Named("llvm.fabs.v4f32")
1395         },
1396         "qabs_s8" => Intrinsic {
1397             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1398             output: &::I8x8,
1399             definition: Named("llvm.neon.vsqabs.v8i8")
1400         },
1401         "qabs_s16" => Intrinsic {
1402             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1403             output: &::I16x4,
1404             definition: Named("llvm.neon.vsqabs.v4i16")
1405         },
1406         "qabs_s32" => Intrinsic {
1407             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1408             output: &::I32x2,
1409             definition: Named("llvm.neon.vsqabs.v2i32")
1410         },
1411         "qabsq_s8" => Intrinsic {
1412             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1413             output: &::I8x16,
1414             definition: Named("llvm.neon.vsqabs.v16i8")
1415         },
1416         "qabsq_s16" => Intrinsic {
1417             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1418             output: &::I16x8,
1419             definition: Named("llvm.neon.vsqabs.v8i16")
1420         },
1421         "qabsq_s32" => Intrinsic {
1422             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1423             output: &::I32x4,
1424             definition: Named("llvm.neon.vsqabs.v4i32")
1425         },
1426         "qneg_s8" => Intrinsic {
1427             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1428             output: &::I8x8,
1429             definition: Named("llvm.neon.vsqneg.v8i8")
1430         },
1431         "qneg_s16" => Intrinsic {
1432             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1433             output: &::I16x4,
1434             definition: Named("llvm.neon.vsqneg.v4i16")
1435         },
1436         "qneg_s32" => Intrinsic {
1437             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1438             output: &::I32x2,
1439             definition: Named("llvm.neon.vsqneg.v2i32")
1440         },
1441         "qnegq_s8" => Intrinsic {
1442             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1443             output: &::I8x16,
1444             definition: Named("llvm.neon.vsqneg.v16i8")
1445         },
1446         "qnegq_s16" => Intrinsic {
1447             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1448             output: &::I16x8,
1449             definition: Named("llvm.neon.vsqneg.v8i16")
1450         },
1451         "qnegq_s32" => Intrinsic {
1452             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1453             output: &::I32x4,
1454             definition: Named("llvm.neon.vsqneg.v4i32")
1455         },
1456         "clz_s8" => Intrinsic {
1457             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1458             output: &::I8x8,
1459             definition: Named("llvm.ctlz.v8i8")
1460         },
1461         "clz_u8" => Intrinsic {
1462             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1463             output: &::U8x8,
1464             definition: Named("llvm.ctlz.v8i8")
1465         },
1466         "clz_s16" => Intrinsic {
1467             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1468             output: &::I16x4,
1469             definition: Named("llvm.ctlz.v4i16")
1470         },
1471         "clz_u16" => Intrinsic {
1472             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1473             output: &::U16x4,
1474             definition: Named("llvm.ctlz.v4i16")
1475         },
1476         "clz_s32" => Intrinsic {
1477             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1478             output: &::I32x2,
1479             definition: Named("llvm.ctlz.v2i32")
1480         },
1481         "clz_u32" => Intrinsic {
1482             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1483             output: &::U32x2,
1484             definition: Named("llvm.ctlz.v2i32")
1485         },
1486         "clzq_s8" => Intrinsic {
1487             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1488             output: &::I8x16,
1489             definition: Named("llvm.ctlz.v16i8")
1490         },
1491         "clzq_u8" => Intrinsic {
1492             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1493             output: &::U8x16,
1494             definition: Named("llvm.ctlz.v16i8")
1495         },
1496         "clzq_s16" => Intrinsic {
1497             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1498             output: &::I16x8,
1499             definition: Named("llvm.ctlz.v8i16")
1500         },
1501         "clzq_u16" => Intrinsic {
1502             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1503             output: &::U16x8,
1504             definition: Named("llvm.ctlz.v8i16")
1505         },
1506         "clzq_s32" => Intrinsic {
1507             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1508             output: &::I32x4,
1509             definition: Named("llvm.ctlz.v4i32")
1510         },
1511         "clzq_u32" => Intrinsic {
1512             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1513             output: &::U32x4,
1514             definition: Named("llvm.ctlz.v4i32")
1515         },
1516         "cls_s8" => Intrinsic {
1517             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1518             output: &::I8x8,
1519             definition: Named("llvm.neon.vcls.v8i8")
1520         },
1521         "cls_u8" => Intrinsic {
1522             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1523             output: &::U8x8,
1524             definition: Named("llvm.neon.vcls.v8i8")
1525         },
1526         "cls_s16" => Intrinsic {
1527             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1528             output: &::I16x4,
1529             definition: Named("llvm.neon.vcls.v4i16")
1530         },
1531         "cls_u16" => Intrinsic {
1532             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1533             output: &::U16x4,
1534             definition: Named("llvm.neon.vcls.v4i16")
1535         },
1536         "cls_s32" => Intrinsic {
1537             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1538             output: &::I32x2,
1539             definition: Named("llvm.neon.vcls.v2i32")
1540         },
1541         "cls_u32" => Intrinsic {
1542             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1543             output: &::U32x2,
1544             definition: Named("llvm.neon.vcls.v2i32")
1545         },
1546         "clsq_s8" => Intrinsic {
1547             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1548             output: &::I8x16,
1549             definition: Named("llvm.neon.vcls.v16i8")
1550         },
1551         "clsq_u8" => Intrinsic {
1552             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1553             output: &::U8x16,
1554             definition: Named("llvm.neon.vcls.v16i8")
1555         },
1556         "clsq_s16" => Intrinsic {
1557             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1558             output: &::I16x8,
1559             definition: Named("llvm.neon.vcls.v8i16")
1560         },
1561         "clsq_u16" => Intrinsic {
1562             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1563             output: &::U16x8,
1564             definition: Named("llvm.neon.vcls.v8i16")
1565         },
1566         "clsq_s32" => Intrinsic {
1567             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1568             output: &::I32x4,
1569             definition: Named("llvm.neon.vcls.v4i32")
1570         },
1571         "clsq_u32" => Intrinsic {
1572             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1573             output: &::U32x4,
1574             definition: Named("llvm.neon.vcls.v4i32")
1575         },
1576         "cnt_s8" => Intrinsic {
1577             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1578             output: &::I8x8,
1579             definition: Named("llvm.ctpop.v8i8")
1580         },
1581         "cnt_u8" => Intrinsic {
1582             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1583             output: &::U8x8,
1584             definition: Named("llvm.ctpop.v8i8")
1585         },
1586         "cntq_s8" => Intrinsic {
1587             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1588             output: &::I8x16,
1589             definition: Named("llvm.ctpop.v16i8")
1590         },
1591         "cntq_u8" => Intrinsic {
1592             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1593             output: &::U8x16,
1594             definition: Named("llvm.ctpop.v16i8")
1595         },
1596         "recpe_u32" => Intrinsic {
1597             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1598             output: &::U32x2,
1599             definition: Named("llvm.neon.vrecpe.v2i32")
1600         },
1601         "recpe_f32" => Intrinsic {
1602             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1603             output: &::F32x2,
1604             definition: Named("llvm.neon.vrecpe.v2f32")
1605         },
1606         "recpeq_u32" => Intrinsic {
1607             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1608             output: &::U32x4,
1609             definition: Named("llvm.neon.vrecpe.v4i32")
1610         },
1611         "recpeq_f32" => Intrinsic {
1612             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1613             output: &::F32x4,
1614             definition: Named("llvm.neon.vrecpe.v4f32")
1615         },
1616         "recps_f32" => Intrinsic {
1617             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1618             output: &::F32x2,
1619             definition: Named("llvm.neon.vfrecps.v2f32")
1620         },
1621         "recpsq_f32" => Intrinsic {
1622             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1623             output: &::F32x4,
1624             definition: Named("llvm.neon.vfrecps.v4f32")
1625         },
1626         "sqrt_f32" => Intrinsic {
1627             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1628             output: &::F32x2,
1629             definition: Named("llvm.sqrt.v2f32")
1630         },
1631         "sqrtq_f32" => Intrinsic {
1632             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1633             output: &::F32x4,
1634             definition: Named("llvm.sqrt.v4f32")
1635         },
1636         "rsqrte_u32" => Intrinsic {
1637             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1638             output: &::U32x2,
1639             definition: Named("llvm.neon.vrsqrte.v2i32")
1640         },
1641         "rsqrte_f32" => Intrinsic {
1642             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1643             output: &::F32x2,
1644             definition: Named("llvm.neon.vrsqrte.v2f32")
1645         },
1646         "rsqrteq_u32" => Intrinsic {
1647             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1648             output: &::U32x4,
1649             definition: Named("llvm.neon.vrsqrte.v4i32")
1650         },
1651         "rsqrteq_f32" => Intrinsic {
1652             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1653             output: &::F32x4,
1654             definition: Named("llvm.neon.vrsqrte.v4f32")
1655         },
1656         "rsqrts_f32" => Intrinsic {
1657             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1658             output: &::F32x2,
1659             definition: Named("llvm.neon.vrsqrts.v2f32")
1660         },
1661         "rsqrtsq_f32" => Intrinsic {
1662             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1663             output: &::F32x4,
1664             definition: Named("llvm.neon.vrsqrts.v4f32")
1665         },
1666         "bsl_s8" => Intrinsic {
1667             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1668             output: &::I8x8,
1669             definition: Named("llvm.neon.vbsl.v8i8")
1670         },
1671         "bsl_u8" => Intrinsic {
1672             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1673             output: &::U8x8,
1674             definition: Named("llvm.neon.vbsl.v8i8")
1675         },
1676         "bsl_s16" => Intrinsic {
1677             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1678             output: &::I16x4,
1679             definition: Named("llvm.neon.vbsl.v4i16")
1680         },
1681         "bsl_u16" => Intrinsic {
1682             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1683             output: &::U16x4,
1684             definition: Named("llvm.neon.vbsl.v4i16")
1685         },
1686         "bsl_s32" => Intrinsic {
1687             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1688             output: &::I32x2,
1689             definition: Named("llvm.neon.vbsl.v2i32")
1690         },
1691         "bsl_u32" => Intrinsic {
1692             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1693             output: &::U32x2,
1694             definition: Named("llvm.neon.vbsl.v2i32")
1695         },
1696         "bsl_s64" => Intrinsic {
1697             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1698             output: &::I64x1,
1699             definition: Named("llvm.neon.vbsl.v1i64")
1700         },
1701         "bsl_u64" => Intrinsic {
1702             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1703             output: &::U64x1,
1704             definition: Named("llvm.neon.vbsl.v1i64")
1705         },
1706         "bslq_s8" => Intrinsic {
1707             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1708             output: &::I8x16,
1709             definition: Named("llvm.neon.vbsl.v16i8")
1710         },
1711         "bslq_u8" => Intrinsic {
1712             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1713             output: &::U8x16,
1714             definition: Named("llvm.neon.vbsl.v16i8")
1715         },
1716         "bslq_s16" => Intrinsic {
1717             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1718             output: &::I16x8,
1719             definition: Named("llvm.neon.vbsl.v8i16")
1720         },
1721         "bslq_u16" => Intrinsic {
1722             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1723             output: &::U16x8,
1724             definition: Named("llvm.neon.vbsl.v8i16")
1725         },
1726         "bslq_s32" => Intrinsic {
1727             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1728             output: &::I32x4,
1729             definition: Named("llvm.neon.vbsl.v4i32")
1730         },
1731         "bslq_u32" => Intrinsic {
1732             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1733             output: &::U32x4,
1734             definition: Named("llvm.neon.vbsl.v4i32")
1735         },
1736         "bslq_s64" => Intrinsic {
1737             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1738             output: &::I64x2,
1739             definition: Named("llvm.neon.vbsl.v2i64")
1740         },
1741         "bslq_u64" => Intrinsic {
1742             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1743             output: &::U64x2,
1744             definition: Named("llvm.neon.vbsl.v2i64")
1745         },
1746         "padd_s8" => Intrinsic {
1747             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1748             output: &::I8x8,
1749             definition: Named("llvm.neon.vpadd.v8i8")
1750         },
1751         "padd_u8" => Intrinsic {
1752             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1753             output: &::U8x8,
1754             definition: Named("llvm.neon.vpadd.v8i8")
1755         },
1756         "padd_s16" => Intrinsic {
1757             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1758             output: &::I16x4,
1759             definition: Named("llvm.neon.vpadd.v4i16")
1760         },
1761         "padd_u16" => Intrinsic {
1762             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1763             output: &::U16x4,
1764             definition: Named("llvm.neon.vpadd.v4i16")
1765         },
1766         "padd_s32" => Intrinsic {
1767             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1768             output: &::I32x2,
1769             definition: Named("llvm.neon.vpadd.v2i32")
1770         },
1771         "padd_u32" => Intrinsic {
1772             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1773             output: &::U32x2,
1774             definition: Named("llvm.neon.vpadd.v2i32")
1775         },
1776         "padd_f32" => Intrinsic {
1777             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1778             output: &::F32x2,
1779             definition: Named("llvm.neon.vpadd.v2f32")
1780         },
1781         "paddl_s16" => Intrinsic {
1782             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1783             output: &::I16x4,
1784             definition: Named("llvm.neon.vpaddls.v4i16.v8i8")
1785         },
1786         "paddl_u16" => Intrinsic {
1787             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1788             output: &::U16x4,
1789             definition: Named("llvm.neon.vpaddlu.v4i16.v8i8")
1790         },
1791         "paddl_s32" => Intrinsic {
1792             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1793             output: &::I32x2,
1794             definition: Named("llvm.neon.vpaddls.v2i32.v4i16")
1795         },
1796         "paddl_u32" => Intrinsic {
1797             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1798             output: &::U32x2,
1799             definition: Named("llvm.neon.vpaddlu.v2i32.v4i16")
1800         },
1801         "paddl_s64" => Intrinsic {
1802             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1803             output: &::I64x1,
1804             definition: Named("llvm.neon.vpaddls.v1i64.v2i32")
1805         },
1806         "paddl_u64" => Intrinsic {
1807             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1808             output: &::U64x1,
1809             definition: Named("llvm.neon.vpaddlu.v1i64.v2i32")
1810         },
1811         "paddlq_s16" => Intrinsic {
1812             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1813             output: &::I16x8,
1814             definition: Named("llvm.neon.vpaddls.v8i16.v16i8")
1815         },
1816         "paddlq_u16" => Intrinsic {
1817             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1818             output: &::U16x8,
1819             definition: Named("llvm.neon.vpaddlu.v8i16.v16i8")
1820         },
1821         "paddlq_s32" => Intrinsic {
1822             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1823             output: &::I32x4,
1824             definition: Named("llvm.neon.vpaddls.v4i32.v8i16")
1825         },
1826         "paddlq_u32" => Intrinsic {
1827             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1828             output: &::U32x4,
1829             definition: Named("llvm.neon.vpaddlu.v4i32.v8i16")
1830         },
1831         "paddlq_s64" => Intrinsic {
1832             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1833             output: &::I64x2,
1834             definition: Named("llvm.neon.vpaddls.v2i64.v4i32")
1835         },
1836         "paddlq_u64" => Intrinsic {
1837             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1838             output: &::U64x2,
1839             definition: Named("llvm.neon.vpaddlu.v2i64.v4i32")
1840         },
1841         "padal_s16" => Intrinsic {
1842             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I8x8]; &INPUTS },
1843             output: &::I16x4,
1844             definition: Named("llvm.neon.vpadals.v4i16.v4i16")
1845         },
1846         "padal_u16" => Intrinsic {
1847             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U8x8]; &INPUTS },
1848             output: &::U16x4,
1849             definition: Named("llvm.neon.vpadalu.v4i16.v4i16")
1850         },
1851         "padal_s32" => Intrinsic {
1852             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I16x4]; &INPUTS },
1853             output: &::I32x2,
1854             definition: Named("llvm.neon.vpadals.v2i32.v2i32")
1855         },
1856         "padal_u32" => Intrinsic {
1857             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U16x4]; &INPUTS },
1858             output: &::U32x2,
1859             definition: Named("llvm.neon.vpadalu.v2i32.v2i32")
1860         },
1861         "padal_s64" => Intrinsic {
1862             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I32x2]; &INPUTS },
1863             output: &::I64x1,
1864             definition: Named("llvm.neon.vpadals.v1i64.v1i64")
1865         },
1866         "padal_u64" => Intrinsic {
1867             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U32x2]; &INPUTS },
1868             output: &::U64x1,
1869             definition: Named("llvm.neon.vpadalu.v1i64.v1i64")
1870         },
1871         "padalq_s16" => Intrinsic {
1872             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I8x16]; &INPUTS },
1873             output: &::I16x8,
1874             definition: Named("llvm.neon.vpadals.v8i16.v8i16")
1875         },
1876         "padalq_u16" => Intrinsic {
1877             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U8x16]; &INPUTS },
1878             output: &::U16x8,
1879             definition: Named("llvm.neon.vpadalu.v8i16.v8i16")
1880         },
1881         "padalq_s32" => Intrinsic {
1882             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I16x8]; &INPUTS },
1883             output: &::I32x4,
1884             definition: Named("llvm.neon.vpadals.v4i32.v4i32")
1885         },
1886         "padalq_u32" => Intrinsic {
1887             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U16x8]; &INPUTS },
1888             output: &::U32x4,
1889             definition: Named("llvm.neon.vpadalu.v4i32.v4i32")
1890         },
1891         "padalq_s64" => Intrinsic {
1892             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I32x4]; &INPUTS },
1893             output: &::I64x2,
1894             definition: Named("llvm.neon.vpadals.v2i64.v2i64")
1895         },
1896         "padalq_u64" => Intrinsic {
1897             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32x4]; &INPUTS },
1898             output: &::U64x2,
1899             definition: Named("llvm.neon.vpadalu.v2i64.v2i64")
1900         },
1901         "pmax_s8" => Intrinsic {
1902             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1903             output: &::I8x8,
1904             definition: Named("llvm.neon.vpmaxs.v8i8")
1905         },
1906         "pmax_u8" => Intrinsic {
1907             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1908             output: &::U8x8,
1909             definition: Named("llvm.neon.vpmaxu.v8i8")
1910         },
1911         "pmax_s16" => Intrinsic {
1912             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1913             output: &::I16x4,
1914             definition: Named("llvm.neon.vpmaxs.v4i16")
1915         },
1916         "pmax_u16" => Intrinsic {
1917             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1918             output: &::U16x4,
1919             definition: Named("llvm.neon.vpmaxu.v4i16")
1920         },
1921         "pmax_s32" => Intrinsic {
1922             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1923             output: &::I32x2,
1924             definition: Named("llvm.neon.vpmaxs.v2i32")
1925         },
1926         "pmax_u32" => Intrinsic {
1927             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1928             output: &::U32x2,
1929             definition: Named("llvm.neon.vpmaxu.v2i32")
1930         },
1931         "pmax_f32" => Intrinsic {
1932             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1933             output: &::F32x2,
1934             definition: Named("llvm.neon.vpmaxf.v2f32")
1935         },
1936         "pmin_s8" => Intrinsic {
1937             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1938             output: &::I8x8,
1939             definition: Named("llvm.neon.vpmins.v8i8")
1940         },
1941         "pmin_u8" => Intrinsic {
1942             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1943             output: &::U8x8,
1944             definition: Named("llvm.neon.vpminu.v8i8")
1945         },
1946         "pmin_s16" => Intrinsic {
1947             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1948             output: &::I16x4,
1949             definition: Named("llvm.neon.vpmins.v4i16")
1950         },
1951         "pmin_u16" => Intrinsic {
1952             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1953             output: &::U16x4,
1954             definition: Named("llvm.neon.vpminu.v4i16")
1955         },
1956         "pmin_s32" => Intrinsic {
1957             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1958             output: &::I32x2,
1959             definition: Named("llvm.neon.vpmins.v2i32")
1960         },
1961         "pmin_u32" => Intrinsic {
1962             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1963             output: &::U32x2,
1964             definition: Named("llvm.neon.vpminu.v2i32")
1965         },
1966         "pmin_f32" => Intrinsic {
1967             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1968             output: &::F32x2,
1969             definition: Named("llvm.neon.vpminf.v2f32")
1970         },
1971         "pminq_s8" => Intrinsic {
1972             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1973             output: &::I8x16,
1974             definition: Named("llvm.neon.vpmins.v16i8")
1975         },
1976         "pminq_u8" => Intrinsic {
1977             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1978             output: &::U8x16,
1979             definition: Named("llvm.neon.vpminu.v16i8")
1980         },
1981         "pminq_s16" => Intrinsic {
1982             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1983             output: &::I16x8,
1984             definition: Named("llvm.neon.vpmins.v8i16")
1985         },
1986         "pminq_u16" => Intrinsic {
1987             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1988             output: &::U16x8,
1989             definition: Named("llvm.neon.vpminu.v8i16")
1990         },
1991         "pminq_s32" => Intrinsic {
1992             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1993             output: &::I32x4,
1994             definition: Named("llvm.neon.vpmins.v4i32")
1995         },
1996         "pminq_u32" => Intrinsic {
1997             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1998             output: &::U32x4,
1999             definition: Named("llvm.neon.vpminu.v4i32")
2000         },
2001         "pminq_f32" => Intrinsic {
2002             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2003             output: &::F32x4,
2004             definition: Named("llvm.neon.vpminf.v4f32")
2005         },
2006         "tbl1_s8" => Intrinsic {
2007             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::U8x8]; &INPUTS },
2008             output: &::I8x8,
2009             definition: Named("llvm.neon.vtbl1")
2010         },
2011         "tbl1_u8" => Intrinsic {
2012             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2013             output: &::U8x8,
2014             definition: Named("llvm.neon.vtbl1")
2015         },
2016         "tbx1_s8" => Intrinsic {
2017             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::U8x8]; &INPUTS },
2018             output: &::I8x8,
2019             definition: Named("llvm.neon.vtbx1")
2020         },
2021         "tbx1_u8" => Intrinsic {
2022             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &INPUTS },
2023             output: &::U8x8,
2024             definition: Named("llvm.neon.vtbx1")
2025         },
2026         "tbl2_s8" => Intrinsic {
2027             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2028             output: &::I8x8,
2029             definition: Named("llvm.neon.vtbl2")
2030         },
2031         "tbl2_u8" => Intrinsic {
2032             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2033             output: &::U8x8,
2034             definition: Named("llvm.neon.vtbl2")
2035         },
2036         "tbx2_s8" => Intrinsic {
2037             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2038             output: &::I8x8,
2039             definition: Named("llvm.neon.vtbx2")
2040         },
2041         "tbx2_u8" => Intrinsic {
2042             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2043             output: &::U8x8,
2044             definition: Named("llvm.neon.vtbx2")
2045         },
2046         "tbl3_s8" => Intrinsic {
2047             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2048             output: &::I8x8,
2049             definition: Named("llvm.neon.vtbl3")
2050         },
2051         "tbl3_u8" => Intrinsic {
2052             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2053             output: &::U8x8,
2054             definition: Named("llvm.neon.vtbl3")
2055         },
2056         "tbx3_s8" => Intrinsic {
2057             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2058             output: &::I8x8,
2059             definition: Named("llvm.neon.vtbx3")
2060         },
2061         "tbx3_u8" => Intrinsic {
2062             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2063             output: &::U8x8,
2064             definition: Named("llvm.neon.vtbx3")
2065         },
2066         "tbl4_s8" => Intrinsic {
2067             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2068             output: &::I8x8,
2069             definition: Named("llvm.neon.vtbl4")
2070         },
2071         "tbl4_u8" => Intrinsic {
2072             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2073             output: &::U8x8,
2074             definition: Named("llvm.neon.vtbl4")
2075         },
2076         "tbx4_s8" => Intrinsic {
2077             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2078             output: &::I8x8,
2079             definition: Named("llvm.neon.vtbx4")
2080         },
2081         "tbx4_u8" => Intrinsic {
2082             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2083             output: &::U8x8,
2084             definition: Named("llvm.neon.vtbx4")
2085         },
2086         _ => return None,
2087     })
2088 }