src/librustc_platform_intrinsics/arm.rs

   1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
   2 // file at the top-level directory of this distribution and at
   3 // http://rust-lang.org/COPYRIGHT.
   4 //
   5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
   6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
   7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
   8 // option. This file may not be copied, modified, or distributed
   9 // except according to those terms.
  10
  11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
  12 // ignore-tidy-linelength
  13
  14 #![allow(unused_imports)]
  15
  16 use {Intrinsic, Type};
  17 use IntrinsicDef::Named;
  18
  19 pub fn find(name: &str) -> Option<Intrinsic> {
  20     if !name.starts_with("arm_v") { return None }
  21     Some(match &name["arm_v".len()..] {
  22         "hadd_s8" => Intrinsic {
  23             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  24             output: &::I8x8,
  25             definition: Named("llvm.arm.neon.vhadds.v8i8")
  26         },
  27         "hadd_u8" => Intrinsic {
  28             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  29             output: &::U8x8,
  30             definition: Named("llvm.arm.neon.vhaddu.v8i8")
  31         },
  32         "hadd_s16" => Intrinsic {
  33             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  34             output: &::I16x4,
  35             definition: Named("llvm.arm.neon.vhadds.v4i16")
  36         },
  37         "hadd_u16" => Intrinsic {
  38             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
  39             output: &::U16x4,
  40             definition: Named("llvm.arm.neon.vhaddu.v4i16")
  41         },
  42         "hadd_s32" => Intrinsic {
  43             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
  44             output: &::I32x2,
  45             definition: Named("llvm.arm.neon.vhadds.v2i32")
  46         },
  47         "hadd_u32" => Intrinsic {
  48             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  49             output: &::U32x2,
  50             definition: Named("llvm.arm.neon.vhaddu.v2i32")
  51         },
  52         "haddq_s8" => Intrinsic {
  53             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
  54             output: &::I8x16,
  55             definition: Named("llvm.arm.neon.vhadds.v16i8")
  56         },
  57         "haddq_u8" => Intrinsic {
  58             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
  59             output: &::U8x16,
  60             definition: Named("llvm.arm.neon.vhaddu.v16i8")
  61         },
  62         "haddq_s16" => Intrinsic {
  63             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
  64             output: &::I16x8,
  65             definition: Named("llvm.arm.neon.vhadds.v8i16")
  66         },
  67         "haddq_u16" => Intrinsic {
  68             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
  69             output: &::U16x8,
  70             definition: Named("llvm.arm.neon.vhaddu.v8i16")
  71         },
  72         "haddq_s32" => Intrinsic {
  73             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
  74             output: &::I32x4,
  75             definition: Named("llvm.arm.neon.vhadds.v4i32")
  76         },
  77         "haddq_u32" => Intrinsic {
  78             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  79             output: &::U32x4,
  80             definition: Named("llvm.arm.neon.vhaddu.v4i32")
  81         },
  82         "rhadd_s8" => Intrinsic {
  83             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  84             output: &::I8x8,
  85             definition: Named("llvm.arm.neon.vrhadds.v8i8")
  86         },
  87         "rhadd_u8" => Intrinsic {
  88             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  89             output: &::U8x8,
  90             definition: Named("llvm.arm.neon.vrhaddu.v8i8")
  91         },
  92         "rhadd_s16" => Intrinsic {
  93             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  94             output: &::I16x4,
  95             definition: Named("llvm.arm.neon.vrhadds.v4i16")
  96         },
  97         "rhadd_u16" => Intrinsic {
  98             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
  99             output: &::U16x4,
 100             definition: Named("llvm.arm.neon.vrhaddu.v4i16")
 101         },
 102         "rhadd_s32" => Intrinsic {
 103             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 104             output: &::I32x2,
 105             definition: Named("llvm.arm.neon.vrhadds.v2i32")
 106         },
 107         "rhadd_u32" => Intrinsic {
 108             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 109             output: &::U32x2,
 110             definition: Named("llvm.arm.neon.vrhaddu.v2i32")
 111         },
 112         "rhaddq_s8" => Intrinsic {
 113             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 114             output: &::I8x16,
 115             definition: Named("llvm.arm.neon.vrhadds.v16i8")
 116         },
 117         "rhaddq_u8" => Intrinsic {
 118             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 119             output: &::U8x16,
 120             definition: Named("llvm.arm.neon.vrhaddu.v16i8")
 121         },
 122         "rhaddq_s16" => Intrinsic {
 123             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 124             output: &::I16x8,
 125             definition: Named("llvm.arm.neon.vrhadds.v8i16")
 126         },
 127         "rhaddq_u16" => Intrinsic {
 128             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 129             output: &::U16x8,
 130             definition: Named("llvm.arm.neon.vrhaddu.v8i16")
 131         },
 132         "rhaddq_s32" => Intrinsic {
 133             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 134             output: &::I32x4,
 135             definition: Named("llvm.arm.neon.vrhadds.v4i32")
 136         },
 137         "rhaddq_u32" => Intrinsic {
 138             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 139             output: &::U32x4,
 140             definition: Named("llvm.arm.neon.vrhaddu.v4i32")
 141         },
 142         "qadd_s8" => Intrinsic {
 143             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 144             output: &::I8x8,
 145             definition: Named("llvm.arm.neon.vqadds.v8i8")
 146         },
 147         "qadd_u8" => Intrinsic {
 148             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 149             output: &::U8x8,
 150             definition: Named("llvm.arm.neon.vqaddu.v8i8")
 151         },
 152         "qadd_s16" => Intrinsic {
 153             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 154             output: &::I16x4,
 155             definition: Named("llvm.arm.neon.vqadds.v4i16")
 156         },
 157         "qadd_u16" => Intrinsic {
 158             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 159             output: &::U16x4,
 160             definition: Named("llvm.arm.neon.vqaddu.v4i16")
 161         },
 162         "qadd_s32" => Intrinsic {
 163             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 164             output: &::I32x2,
 165             definition: Named("llvm.arm.neon.vqadds.v2i32")
 166         },
 167         "qadd_u32" => Intrinsic {
 168             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 169             output: &::U32x2,
 170             definition: Named("llvm.arm.neon.vqaddu.v2i32")
 171         },
 172         "qadd_s64" => Intrinsic {
 173             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 174             output: &::I64x1,
 175             definition: Named("llvm.arm.neon.vqadds.v1i64")
 176         },
 177         "qadd_u64" => Intrinsic {
 178             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 179             output: &::U64x1,
 180             definition: Named("llvm.arm.neon.vqaddu.v1i64")
 181         },
 182         "qaddq_s8" => Intrinsic {
 183             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 184             output: &::I8x16,
 185             definition: Named("llvm.arm.neon.vqadds.v16i8")
 186         },
 187         "qaddq_u8" => Intrinsic {
 188             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 189             output: &::U8x16,
 190             definition: Named("llvm.arm.neon.vqaddu.v16i8")
 191         },
 192         "qaddq_s16" => Intrinsic {
 193             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 194             output: &::I16x8,
 195             definition: Named("llvm.arm.neon.vqadds.v8i16")
 196         },
 197         "qaddq_u16" => Intrinsic {
 198             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 199             output: &::U16x8,
 200             definition: Named("llvm.arm.neon.vqaddu.v8i16")
 201         },
 202         "qaddq_s32" => Intrinsic {
 203             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 204             output: &::I32x4,
 205             definition: Named("llvm.arm.neon.vqadds.v4i32")
 206         },
 207         "qaddq_u32" => Intrinsic {
 208             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 209             output: &::U32x4,
 210             definition: Named("llvm.arm.neon.vqaddu.v4i32")
 211         },
 212         "qaddq_s64" => Intrinsic {
 213             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 214             output: &::I64x2,
 215             definition: Named("llvm.arm.neon.vqadds.v2i64")
 216         },
 217         "qaddq_u64" => Intrinsic {
 218             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 219             output: &::U64x2,
 220             definition: Named("llvm.arm.neon.vqaddu.v2i64")
 221         },
 222         "raddhn_s16" => Intrinsic {
 223             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 224             output: &::I8x8,
 225             definition: Named("llvm.arm.neon.vraddhn.v8i8")
 226         },
 227         "raddhn_u16" => Intrinsic {
 228             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 229             output: &::U8x8,
 230             definition: Named("llvm.arm.neon.vraddhn.v8i8")
 231         },
 232         "raddhn_s32" => Intrinsic {
 233             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 234             output: &::I16x4,
 235             definition: Named("llvm.arm.neon.vraddhn.v4i16")
 236         },
 237         "raddhn_u32" => Intrinsic {
 238             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 239             output: &::U16x4,
 240             definition: Named("llvm.arm.neon.vraddhn.v4i16")
 241         },
 242         "raddhn_s64" => Intrinsic {
 243             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 244             output: &::I32x2,
 245             definition: Named("llvm.arm.neon.vraddhn.v2i32")
 246         },
 247         "raddhn_u64" => Intrinsic {
 248             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 249             output: &::U32x2,
 250             definition: Named("llvm.arm.neon.vraddhn.v2i32")
 251         },
 252         "fma_f32" => Intrinsic {
 253             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 254             output: &::F32x2,
 255             definition: Named("llvm.fma.v2f32")
 256         },
 257         "fmaq_f32" => Intrinsic {
 258             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 259             output: &::F32x4,
 260             definition: Named("llvm.fma.v4f32")
 261         },
 262         "qdmulh_s16" => Intrinsic {
 263             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 264             output: &::I16x4,
 265             definition: Named("llvm.arm.neon.vsqdmulh.v4i16")
 266         },
 267         "qdmulh_s32" => Intrinsic {
 268             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 269             output: &::I32x2,
 270             definition: Named("llvm.arm.neon.vsqdmulh.v2i32")
 271         },
 272         "qdmulhq_s16" => Intrinsic {
 273             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 274             output: &::I16x8,
 275             definition: Named("llvm.arm.neon.vsqdmulh.v8i16")
 276         },
 277         "qdmulhq_s32" => Intrinsic {
 278             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 279             output: &::I32x4,
 280             definition: Named("llvm.arm.neon.vsqdmulh.v4i32")
 281         },
 282         "qrdmulh_s16" => Intrinsic {
 283             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 284             output: &::I16x4,
 285             definition: Named("llvm.arm.neon.vsqrdmulh.v4i16")
 286         },
 287         "qrdmulh_s32" => Intrinsic {
 288             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 289             output: &::I32x2,
 290             definition: Named("llvm.arm.neon.vsqrdmulh.v2i32")
 291         },
 292         "qrdmulhq_s16" => Intrinsic {
 293             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 294             output: &::I16x8,
 295             definition: Named("llvm.arm.neon.vsqrdmulh.v8i16")
 296         },
 297         "qrdmulhq_s32" => Intrinsic {
 298             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 299             output: &::I32x4,
 300             definition: Named("llvm.arm.neon.vsqrdmulh.v4i32")
 301         },
 302         "mull_s8" => Intrinsic {
 303             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 304             output: &::I16x8,
 305             definition: Named("llvm.arm.neon.vmulls.v8i16")
 306         },
 307         "mull_u8" => Intrinsic {
 308             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 309             output: &::U16x8,
 310             definition: Named("llvm.arm.neon.vmullu.v8i16")
 311         },
 312         "mull_s16" => Intrinsic {
 313             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 314             output: &::I32x4,
 315             definition: Named("llvm.arm.neon.vmulls.v4i32")
 316         },
 317         "mull_u16" => Intrinsic {
 318             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 319             output: &::U32x4,
 320             definition: Named("llvm.arm.neon.vmullu.v4i32")
 321         },
 322         "mull_s32" => Intrinsic {
 323             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 324             output: &::I64x2,
 325             definition: Named("llvm.arm.neon.vmulls.v2i64")
 326         },
 327         "mull_u32" => Intrinsic {
 328             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 329             output: &::U64x2,
 330             definition: Named("llvm.arm.neon.vmullu.v2i64")
 331         },
 332         "qdmullq_s8" => Intrinsic {
 333             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 334             output: &::I16x8,
 335             definition: Named("llvm.arm.neon.vsqdmull.v8i16")
 336         },
 337         "qdmullq_s16" => Intrinsic {
 338             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 339             output: &::I32x4,
 340             definition: Named("llvm.arm.neon.vsqdmull.v4i32")
 341         },
 342         "hsub_s8" => Intrinsic {
 343             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 344             output: &::I8x8,
 345             definition: Named("llvm.arm.neon.vhsubs.v8i8")
 346         },
 347         "hsub_u8" => Intrinsic {
 348             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 349             output: &::U8x8,
 350             definition: Named("llvm.arm.neon.vhsubu.v8i8")
 351         },
 352         "hsub_s16" => Intrinsic {
 353             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 354             output: &::I16x4,
 355             definition: Named("llvm.arm.neon.vhsubs.v4i16")
 356         },
 357         "hsub_u16" => Intrinsic {
 358             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 359             output: &::U16x4,
 360             definition: Named("llvm.arm.neon.vhsubu.v4i16")
 361         },
 362         "hsub_s32" => Intrinsic {
 363             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 364             output: &::I32x2,
 365             definition: Named("llvm.arm.neon.vhsubs.v2i32")
 366         },
 367         "hsub_u32" => Intrinsic {
 368             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 369             output: &::U32x2,
 370             definition: Named("llvm.arm.neon.vhsubu.v2i32")
 371         },
 372         "hsubq_s8" => Intrinsic {
 373             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 374             output: &::I8x16,
 375             definition: Named("llvm.arm.neon.vhsubs.v16i8")
 376         },
 377         "hsubq_u8" => Intrinsic {
 378             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 379             output: &::U8x16,
 380             definition: Named("llvm.arm.neon.vhsubu.v16i8")
 381         },
 382         "hsubq_s16" => Intrinsic {
 383             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 384             output: &::I16x8,
 385             definition: Named("llvm.arm.neon.vhsubs.v8i16")
 386         },
 387         "hsubq_u16" => Intrinsic {
 388             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 389             output: &::U16x8,
 390             definition: Named("llvm.arm.neon.vhsubu.v8i16")
 391         },
 392         "hsubq_s32" => Intrinsic {
 393             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 394             output: &::I32x4,
 395             definition: Named("llvm.arm.neon.vhsubs.v4i32")
 396         },
 397         "hsubq_u32" => Intrinsic {
 398             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 399             output: &::U32x4,
 400             definition: Named("llvm.arm.neon.vhsubu.v4i32")
 401         },
 402         "qsub_s8" => Intrinsic {
 403             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 404             output: &::I8x8,
 405             definition: Named("llvm.arm.neon.vqsubs.v8i8")
 406         },
 407         "qsub_u8" => Intrinsic {
 408             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 409             output: &::U8x8,
 410             definition: Named("llvm.arm.neon.vqsubu.v8i8")
 411         },
 412         "qsub_s16" => Intrinsic {
 413             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 414             output: &::I16x4,
 415             definition: Named("llvm.arm.neon.vqsubs.v4i16")
 416         },
 417         "qsub_u16" => Intrinsic {
 418             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 419             output: &::U16x4,
 420             definition: Named("llvm.arm.neon.vqsubu.v4i16")
 421         },
 422         "qsub_s32" => Intrinsic {
 423             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 424             output: &::I32x2,
 425             definition: Named("llvm.arm.neon.vqsubs.v2i32")
 426         },
 427         "qsub_u32" => Intrinsic {
 428             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 429             output: &::U32x2,
 430             definition: Named("llvm.arm.neon.vqsubu.v2i32")
 431         },
 432         "qsub_s64" => Intrinsic {
 433             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 434             output: &::I64x1,
 435             definition: Named("llvm.arm.neon.vqsubs.v1i64")
 436         },
 437         "qsub_u64" => Intrinsic {
 438             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 439             output: &::U64x1,
 440             definition: Named("llvm.arm.neon.vqsubu.v1i64")
 441         },
 442         "qsubq_s8" => Intrinsic {
 443             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 444             output: &::I8x16,
 445             definition: Named("llvm.arm.neon.vqsubs.v16i8")
 446         },
 447         "qsubq_u8" => Intrinsic {
 448             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 449             output: &::U8x16,
 450             definition: Named("llvm.arm.neon.vqsubu.v16i8")
 451         },
 452         "qsubq_s16" => Intrinsic {
 453             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 454             output: &::I16x8,
 455             definition: Named("llvm.arm.neon.vqsubs.v8i16")
 456         },
 457         "qsubq_u16" => Intrinsic {
 458             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 459             output: &::U16x8,
 460             definition: Named("llvm.arm.neon.vqsubu.v8i16")
 461         },
 462         "qsubq_s32" => Intrinsic {
 463             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 464             output: &::I32x4,
 465             definition: Named("llvm.arm.neon.vqsubs.v4i32")
 466         },
 467         "qsubq_u32" => Intrinsic {
 468             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 469             output: &::U32x4,
 470             definition: Named("llvm.arm.neon.vqsubu.v4i32")
 471         },
 472         "qsubq_s64" => Intrinsic {
 473             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 474             output: &::I64x2,
 475             definition: Named("llvm.arm.neon.vqsubs.v2i64")
 476         },
 477         "qsubq_u64" => Intrinsic {
 478             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 479             output: &::U64x2,
 480             definition: Named("llvm.arm.neon.vqsubu.v2i64")
 481         },
 482         "rsubhn_s16" => Intrinsic {
 483             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 484             output: &::I8x8,
 485             definition: Named("llvm.arm.neon.vrsubhn.v8i8")
 486         },
 487         "rsubhn_u16" => Intrinsic {
 488             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 489             output: &::U8x8,
 490             definition: Named("llvm.arm.neon.vrsubhn.v8i8")
 491         },
 492         "rsubhn_s32" => Intrinsic {
 493             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 494             output: &::I16x4,
 495             definition: Named("llvm.arm.neon.vrsubhn.v4i16")
 496         },
 497         "rsubhn_u32" => Intrinsic {
 498             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 499             output: &::U16x4,
 500             definition: Named("llvm.arm.neon.vrsubhn.v4i16")
 501         },
 502         "rsubhn_s64" => Intrinsic {
 503             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 504             output: &::I32x2,
 505             definition: Named("llvm.arm.neon.vrsubhn.v2i32")
 506         },
 507         "rsubhn_u64" => Intrinsic {
 508             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 509             output: &::U32x2,
 510             definition: Named("llvm.arm.neon.vrsubhn.v2i32")
 511         },
 512         "abd_s8" => Intrinsic {
 513             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 514             output: &::I8x8,
 515             definition: Named("llvm.arm.neon.vabds.v8i8")
 516         },
 517         "abd_u8" => Intrinsic {
 518             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 519             output: &::U8x8,
 520             definition: Named("llvm.arm.neon.vabdu.v8i8")
 521         },
 522         "abd_s16" => Intrinsic {
 523             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 524             output: &::I16x4,
 525             definition: Named("llvm.arm.neon.vabds.v4i16")
 526         },
 527         "abd_u16" => Intrinsic {
 528             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 529             output: &::U16x4,
 530             definition: Named("llvm.arm.neon.vabdu.v4i16")
 531         },
 532         "abd_s32" => Intrinsic {
 533             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 534             output: &::I32x2,
 535             definition: Named("llvm.arm.neon.vabds.v2i32")
 536         },
 537         "abd_u32" => Intrinsic {
 538             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 539             output: &::U32x2,
 540             definition: Named("llvm.arm.neon.vabdu.v2i32")
 541         },
 542         "abd_f32" => Intrinsic {
 543             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 544             output: &::F32x2,
 545             definition: Named("llvm.arm.neon.vabdf.v2f32")
 546         },
 547         "abdq_s8" => Intrinsic {
 548             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 549             output: &::I8x16,
 550             definition: Named("llvm.arm.neon.vabds.v16i8")
 551         },
 552         "abdq_u8" => Intrinsic {
 553             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 554             output: &::U8x16,
 555             definition: Named("llvm.arm.neon.vabdu.v16i8")
 556         },
 557         "abdq_s16" => Intrinsic {
 558             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 559             output: &::I16x8,
 560             definition: Named("llvm.arm.neon.vabds.v8i16")
 561         },
 562         "abdq_u16" => Intrinsic {
 563             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 564             output: &::U16x8,
 565             definition: Named("llvm.arm.neon.vabdu.v8i16")
 566         },
 567         "abdq_s32" => Intrinsic {
 568             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 569             output: &::I32x4,
 570             definition: Named("llvm.arm.neon.vabds.v4i32")
 571         },
 572         "abdq_u32" => Intrinsic {
 573             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 574             output: &::U32x4,
 575             definition: Named("llvm.arm.neon.vabdu.v4i32")
 576         },
 577         "abdq_f32" => Intrinsic {
 578             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 579             output: &::F32x4,
 580             definition: Named("llvm.arm.neon.vabdf.v4f32")
 581         },
 582         "max_s8" => Intrinsic {
 583             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 584             output: &::I8x8,
 585             definition: Named("llvm.arm.neon.vmaxs.v8i8")
 586         },
 587         "max_u8" => Intrinsic {
 588             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 589             output: &::U8x8,
 590             definition: Named("llvm.arm.neon.vmaxu.v8i8")
 591         },
 592         "max_s16" => Intrinsic {
 593             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 594             output: &::I16x4,
 595             definition: Named("llvm.arm.neon.vmaxs.v4i16")
 596         },
 597         "max_u16" => Intrinsic {
 598             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 599             output: &::U16x4,
 600             definition: Named("llvm.arm.neon.vmaxu.v4i16")
 601         },
 602         "max_s32" => Intrinsic {
 603             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 604             output: &::I32x2,
 605             definition: Named("llvm.arm.neon.vmaxs.v2i32")
 606         },
 607         "max_u32" => Intrinsic {
 608             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 609             output: &::U32x2,
 610             definition: Named("llvm.arm.neon.vmaxu.v2i32")
 611         },
 612         "max_f32" => Intrinsic {
 613             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 614             output: &::F32x2,
 615             definition: Named("llvm.arm.neon.vmaxf.v2f32")
 616         },
 617         "maxq_s8" => Intrinsic {
 618             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 619             output: &::I8x16,
 620             definition: Named("llvm.arm.neon.vmaxs.v16i8")
 621         },
 622         "maxq_u8" => Intrinsic {
 623             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 624             output: &::U8x16,
 625             definition: Named("llvm.arm.neon.vmaxu.v16i8")
 626         },
 627         "maxq_s16" => Intrinsic {
 628             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 629             output: &::I16x8,
 630             definition: Named("llvm.arm.neon.vmaxs.v8i16")
 631         },
 632         "maxq_u16" => Intrinsic {
 633             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 634             output: &::U16x8,
 635             definition: Named("llvm.arm.neon.vmaxu.v8i16")
 636         },
 637         "maxq_s32" => Intrinsic {
 638             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 639             output: &::I32x4,
 640             definition: Named("llvm.arm.neon.vmaxs.v4i32")
 641         },
 642         "maxq_u32" => Intrinsic {
 643             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 644             output: &::U32x4,
 645             definition: Named("llvm.arm.neon.vmaxu.v4i32")
 646         },
 647         "maxq_f32" => Intrinsic {
 648             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 649             output: &::F32x4,
 650             definition: Named("llvm.arm.neon.vmaxf.v4f32")
 651         },
 652         "min_s8" => Intrinsic {
 653             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 654             output: &::I8x8,
 655             definition: Named("llvm.arm.neon.vmins.v8i8")
 656         },
 657         "min_u8" => Intrinsic {
 658             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 659             output: &::U8x8,
 660             definition: Named("llvm.arm.neon.vminu.v8i8")
 661         },
 662         "min_s16" => Intrinsic {
 663             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 664             output: &::I16x4,
 665             definition: Named("llvm.arm.neon.vmins.v4i16")
 666         },
 667         "min_u16" => Intrinsic {
 668             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 669             output: &::U16x4,
 670             definition: Named("llvm.arm.neon.vminu.v4i16")
 671         },
 672         "min_s32" => Intrinsic {
 673             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 674             output: &::I32x2,
 675             definition: Named("llvm.arm.neon.vmins.v2i32")
 676         },
 677         "min_u32" => Intrinsic {
 678             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 679             output: &::U32x2,
 680             definition: Named("llvm.arm.neon.vminu.v2i32")
 681         },
 682         "min_f32" => Intrinsic {
 683             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 684             output: &::F32x2,
 685             definition: Named("llvm.arm.neon.vminf.v2f32")
 686         },
 687         "minq_s8" => Intrinsic {
 688             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 689             output: &::I8x16,
 690             definition: Named("llvm.arm.neon.vmins.v16i8")
 691         },
 692         "minq_u8" => Intrinsic {
 693             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 694             output: &::U8x16,
 695             definition: Named("llvm.arm.neon.vminu.v16i8")
 696         },
 697         "minq_s16" => Intrinsic {
 698             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 699             output: &::I16x8,
 700             definition: Named("llvm.arm.neon.vmins.v8i16")
 701         },
 702         "minq_u16" => Intrinsic {
 703             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 704             output: &::U16x8,
 705             definition: Named("llvm.arm.neon.vminu.v8i16")
 706         },
 707         "minq_s32" => Intrinsic {
 708             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 709             output: &::I32x4,
 710             definition: Named("llvm.arm.neon.vmins.v4i32")
 711         },
 712         "minq_u32" => Intrinsic {
 713             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 714             output: &::U32x4,
 715             definition: Named("llvm.arm.neon.vminu.v4i32")
 716         },
 717         "minq_f32" => Intrinsic {
 718             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 719             output: &::F32x4,
 720             definition: Named("llvm.arm.neon.vminf.v4f32")
 721         },
 722         "shl_s8" => Intrinsic {
 723             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 724             output: &::I8x8,
 725             definition: Named("llvm.arm.neon.vshls.v8i8")
 726         },
 727         "shl_u8" => Intrinsic {
 728             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 729             output: &::U8x8,
 730             definition: Named("llvm.arm.neon.vshlu.v8i8")
 731         },
 732         "shl_s16" => Intrinsic {
 733             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 734             output: &::I16x4,
 735             definition: Named("llvm.arm.neon.vshls.v4i16")
 736         },
 737         "shl_u16" => Intrinsic {
 738             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 739             output: &::U16x4,
 740             definition: Named("llvm.arm.neon.vshlu.v4i16")
 741         },
 742         "shl_s32" => Intrinsic {
 743             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 744             output: &::I32x2,
 745             definition: Named("llvm.arm.neon.vshls.v2i32")
 746         },
 747         "shl_u32" => Intrinsic {
 748             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 749             output: &::U32x2,
 750             definition: Named("llvm.arm.neon.vshlu.v2i32")
 751         },
 752         "shl_s64" => Intrinsic {
 753             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 754             output: &::I64x1,
 755             definition: Named("llvm.arm.neon.vshls.v1i64")
 756         },
 757         "shl_u64" => Intrinsic {
 758             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 759             output: &::U64x1,
 760             definition: Named("llvm.arm.neon.vshlu.v1i64")
 761         },
 762         "shlq_s8" => Intrinsic {
 763             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 764             output: &::I8x16,
 765             definition: Named("llvm.arm.neon.vshls.v16i8")
 766         },
 767         "shlq_u8" => Intrinsic {
 768             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 769             output: &::U8x16,
 770             definition: Named("llvm.arm.neon.vshlu.v16i8")
 771         },
 772         "shlq_s16" => Intrinsic {
 773             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 774             output: &::I16x8,
 775             definition: Named("llvm.arm.neon.vshls.v8i16")
 776         },
 777         "shlq_u16" => Intrinsic {
 778             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 779             output: &::U16x8,
 780             definition: Named("llvm.arm.neon.vshlu.v8i16")
 781         },
 782         "shlq_s32" => Intrinsic {
 783             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 784             output: &::I32x4,
 785             definition: Named("llvm.arm.neon.vshls.v4i32")
 786         },
 787         "shlq_u32" => Intrinsic {
 788             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 789             output: &::U32x4,
 790             definition: Named("llvm.arm.neon.vshlu.v4i32")
 791         },
 792         "shlq_s64" => Intrinsic {
 793             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 794             output: &::I64x2,
 795             definition: Named("llvm.arm.neon.vshls.v2i64")
 796         },
 797         "shlq_u64" => Intrinsic {
 798             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 799             output: &::U64x2,
 800             definition: Named("llvm.arm.neon.vshlu.v2i64")
 801         },
 802         "qshl_s8" => Intrinsic {
 803             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 804             output: &::I8x8,
 805             definition: Named("llvm.arm.neon.vqshls.v8i8")
 806         },
 807         "qshl_u8" => Intrinsic {
 808             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 809             output: &::U8x8,
 810             definition: Named("llvm.arm.neon.vqshlu.v8i8")
 811         },
 812         "qshl_s16" => Intrinsic {
 813             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 814             output: &::I16x4,
 815             definition: Named("llvm.arm.neon.vqshls.v4i16")
 816         },
 817         "qshl_u16" => Intrinsic {
 818             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 819             output: &::U16x4,
 820             definition: Named("llvm.arm.neon.vqshlu.v4i16")
 821         },
 822         "qshl_s32" => Intrinsic {
 823             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 824             output: &::I32x2,
 825             definition: Named("llvm.arm.neon.vqshls.v2i32")
 826         },
 827         "qshl_u32" => Intrinsic {
 828             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 829             output: &::U32x2,
 830             definition: Named("llvm.arm.neon.vqshlu.v2i32")
 831         },
 832         "qshl_s64" => Intrinsic {
 833             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 834             output: &::I64x1,
 835             definition: Named("llvm.arm.neon.vqshls.v1i64")
 836         },
 837         "qshl_u64" => Intrinsic {
 838             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 839             output: &::U64x1,
 840             definition: Named("llvm.arm.neon.vqshlu.v1i64")
 841         },
 842         "qshlq_s8" => Intrinsic {
 843             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 844             output: &::I8x16,
 845             definition: Named("llvm.arm.neon.vqshls.v16i8")
 846         },
 847         "qshlq_u8" => Intrinsic {
 848             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 849             output: &::U8x16,
 850             definition: Named("llvm.arm.neon.vqshlu.v16i8")
 851         },
 852         "qshlq_s16" => Intrinsic {
 853             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 854             output: &::I16x8,
 855             definition: Named("llvm.arm.neon.vqshls.v8i16")
 856         },
 857         "qshlq_u16" => Intrinsic {
 858             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 859             output: &::U16x8,
 860             definition: Named("llvm.arm.neon.vqshlu.v8i16")
 861         },
 862         "qshlq_s32" => Intrinsic {
 863             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 864             output: &::I32x4,
 865             definition: Named("llvm.arm.neon.vqshls.v4i32")
 866         },
 867         "qshlq_u32" => Intrinsic {
 868             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 869             output: &::U32x4,
 870             definition: Named("llvm.arm.neon.vqshlu.v4i32")
 871         },
 872         "qshlq_s64" => Intrinsic {
 873             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 874             output: &::I64x2,
 875             definition: Named("llvm.arm.neon.vqshls.v2i64")
 876         },
 877         "qshlq_u64" => Intrinsic {
 878             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 879             output: &::U64x2,
 880             definition: Named("llvm.arm.neon.vqshlu.v2i64")
 881         },
 882         "rshl_s8" => Intrinsic {
 883             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 884             output: &::I8x8,
 885             definition: Named("llvm.arm.neon.vrshls.v8i8")
 886         },
 887         "rshl_u8" => Intrinsic {
 888             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 889             output: &::U8x8,
 890             definition: Named("llvm.arm.neon.vrshlu.v8i8")
 891         },
 892         "rshl_s16" => Intrinsic {
 893             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 894             output: &::I16x4,
 895             definition: Named("llvm.arm.neon.vrshls.v4i16")
 896         },
 897         "rshl_u16" => Intrinsic {
 898             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 899             output: &::U16x4,
 900             definition: Named("llvm.arm.neon.vrshlu.v4i16")
 901         },
 902         "rshl_s32" => Intrinsic {
 903             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 904             output: &::I32x2,
 905             definition: Named("llvm.arm.neon.vrshls.v2i32")
 906         },
 907         "rshl_u32" => Intrinsic {
 908             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 909             output: &::U32x2,
 910             definition: Named("llvm.arm.neon.vrshlu.v2i32")
 911         },
 912         "rshl_s64" => Intrinsic {
 913             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 914             output: &::I64x1,
 915             definition: Named("llvm.arm.neon.vrshls.v1i64")
 916         },
 917         "rshl_u64" => Intrinsic {
 918             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 919             output: &::U64x1,
 920             definition: Named("llvm.arm.neon.vrshlu.v1i64")
 921         },
 922         "rshlq_s8" => Intrinsic {
 923             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 924             output: &::I8x16,
 925             definition: Named("llvm.arm.neon.vrshls.v16i8")
 926         },
 927         "rshlq_u8" => Intrinsic {
 928             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 929             output: &::U8x16,
 930             definition: Named("llvm.arm.neon.vrshlu.v16i8")
 931         },
 932         "rshlq_s16" => Intrinsic {
 933             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 934             output: &::I16x8,
 935             definition: Named("llvm.arm.neon.vrshls.v8i16")
 936         },
 937         "rshlq_u16" => Intrinsic {
 938             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 939             output: &::U16x8,
 940             definition: Named("llvm.arm.neon.vrshlu.v8i16")
 941         },
 942         "rshlq_s32" => Intrinsic {
 943             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 944             output: &::I32x4,
 945             definition: Named("llvm.arm.neon.vrshls.v4i32")
 946         },
 947         "rshlq_u32" => Intrinsic {
 948             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 949             output: &::U32x4,
 950             definition: Named("llvm.arm.neon.vrshlu.v4i32")
 951         },
 952         "rshlq_s64" => Intrinsic {
 953             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 954             output: &::I64x2,
 955             definition: Named("llvm.arm.neon.vrshls.v2i64")
 956         },
 957         "rshlq_u64" => Intrinsic {
 958             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 959             output: &::U64x2,
 960             definition: Named("llvm.arm.neon.vrshlu.v2i64")
 961         },
 962         "qrshl_s8" => Intrinsic {
 963             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 964             output: &::I8x8,
 965             definition: Named("llvm.arm.neon.vqrshls.v8i8")
 966         },
 967         "qrshl_u8" => Intrinsic {
 968             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 969             output: &::U8x8,
 970             definition: Named("llvm.arm.neon.vqrshlu.v8i8")
 971         },
 972         "qrshl_s16" => Intrinsic {
 973             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 974             output: &::I16x4,
 975             definition: Named("llvm.arm.neon.vqrshls.v4i16")
 976         },
 977         "qrshl_u16" => Intrinsic {
 978             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 979             output: &::U16x4,
 980             definition: Named("llvm.arm.neon.vqrshlu.v4i16")
 981         },
 982         "qrshl_s32" => Intrinsic {
 983             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 984             output: &::I32x2,
 985             definition: Named("llvm.arm.neon.vqrshls.v2i32")
 986         },
 987         "qrshl_u32" => Intrinsic {
 988             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 989             output: &::U32x2,
 990             definition: Named("llvm.arm.neon.vqrshlu.v2i32")
 991         },
 992         "qrshl_s64" => Intrinsic {
 993             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 994             output: &::I64x1,
 995             definition: Named("llvm.arm.neon.vqrshls.v1i64")
 996         },
 997         "qrshl_u64" => Intrinsic {
 998             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 999             output: &::U64x1,
1000             definition: Named("llvm.arm.neon.vqrshlu.v1i64")
1001         },
1002         "qrshlq_s8" => Intrinsic {
1003             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1004             output: &::I8x16,
1005             definition: Named("llvm.arm.neon.vqrshls.v16i8")
1006         },
1007         "qrshlq_u8" => Intrinsic {
1008             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1009             output: &::U8x16,
1010             definition: Named("llvm.arm.neon.vqrshlu.v16i8")
1011         },
1012         "qrshlq_s16" => Intrinsic {
1013             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1014             output: &::I16x8,
1015             definition: Named("llvm.arm.neon.vqrshls.v8i16")
1016         },
1017         "qrshlq_u16" => Intrinsic {
1018             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1019             output: &::U16x8,
1020             definition: Named("llvm.arm.neon.vqrshlu.v8i16")
1021         },
1022         "qrshlq_s32" => Intrinsic {
1023             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1024             output: &::I32x4,
1025             definition: Named("llvm.arm.neon.vqrshls.v4i32")
1026         },
1027         "qrshlq_u32" => Intrinsic {
1028             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1029             output: &::U32x4,
1030             definition: Named("llvm.arm.neon.vqrshlu.v4i32")
1031         },
1032         "qrshlq_s64" => Intrinsic {
1033             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1034             output: &::I64x2,
1035             definition: Named("llvm.arm.neon.vqrshls.v2i64")
1036         },
1037         "qrshlq_u64" => Intrinsic {
1038             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1039             output: &::U64x2,
1040             definition: Named("llvm.arm.neon.vqrshlu.v2i64")
1041         },
1042         "qshrun_n_s16" => Intrinsic {
1043             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1044             output: &::I8x8,
1045             definition: Named("llvm.arm.neon.vsqshrun.v8i8")
1046         },
1047         "qshrun_n_s32" => Intrinsic {
1048             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1049             output: &::I16x4,
1050             definition: Named("llvm.arm.neon.vsqshrun.v4i16")
1051         },
1052         "qshrun_n_s64" => Intrinsic {
1053             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1054             output: &::I32x2,
1055             definition: Named("llvm.arm.neon.vsqshrun.v2i32")
1056         },
1057         "qrshrun_n_s16" => Intrinsic {
1058             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1059             output: &::I8x8,
1060             definition: Named("llvm.arm.neon.vsqrshrun.v8i8")
1061         },
1062         "qrshrun_n_s32" => Intrinsic {
1063             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1064             output: &::I16x4,
1065             definition: Named("llvm.arm.neon.vsqrshrun.v4i16")
1066         },
1067         "qrshrun_n_s64" => Intrinsic {
1068             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1069             output: &::I32x2,
1070             definition: Named("llvm.arm.neon.vsqrshrun.v2i32")
1071         },
1072         "qshrn_n_s16" => Intrinsic {
1073             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1074             output: &::I8x8,
1075             definition: Named("llvm.arm.neon.vqshrns.v8i8")
1076         },
1077         "qshrn_n_u16" => Intrinsic {
1078             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1079             output: &::U8x8,
1080             definition: Named("llvm.arm.neon.vqshrnu.v8i8")
1081         },
1082         "qshrn_n_s32" => Intrinsic {
1083             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1084             output: &::I16x4,
1085             definition: Named("llvm.arm.neon.vqshrns.v4i16")
1086         },
1087         "qshrn_n_u32" => Intrinsic {
1088             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1089             output: &::U16x4,
1090             definition: Named("llvm.arm.neon.vqshrnu.v4i16")
1091         },
1092         "qshrn_n_s64" => Intrinsic {
1093             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1094             output: &::I32x2,
1095             definition: Named("llvm.arm.neon.vqshrns.v2i32")
1096         },
1097         "qshrn_n_u64" => Intrinsic {
1098             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1099             output: &::U32x2,
1100             definition: Named("llvm.arm.neon.vqshrnu.v2i32")
1101         },
1102         "rshrn_n_s16" => Intrinsic {
1103             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1104             output: &::I8x8,
1105             definition: Named("llvm.arm.neon.vrshrn.v8i8")
1106         },
1107         "rshrn_n_u16" => Intrinsic {
1108             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1109             output: &::U8x8,
1110             definition: Named("llvm.arm.neon.vrshrn.v8i8")
1111         },
1112         "rshrn_n_s32" => Intrinsic {
1113             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1114             output: &::I16x4,
1115             definition: Named("llvm.arm.neon.vrshrn.v4i16")
1116         },
1117         "rshrn_n_u32" => Intrinsic {
1118             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1119             output: &::U16x4,
1120             definition: Named("llvm.arm.neon.vrshrn.v4i16")
1121         },
1122         "rshrn_n_s64" => Intrinsic {
1123             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1124             output: &::I32x2,
1125             definition: Named("llvm.arm.neon.vrshrn.v2i32")
1126         },
1127         "rshrn_n_u64" => Intrinsic {
1128             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1129             output: &::U32x2,
1130             definition: Named("llvm.arm.neon.vrshrn.v2i32")
1131         },
1132         "qrshrn_n_s16" => Intrinsic {
1133             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1134             output: &::I8x8,
1135             definition: Named("llvm.arm.neon.vqrshrns.v8i8")
1136         },
1137         "qrshrn_n_u16" => Intrinsic {
1138             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1139             output: &::U8x8,
1140             definition: Named("llvm.arm.neon.vqrshrnu.v8i8")
1141         },
1142         "qrshrn_n_s32" => Intrinsic {
1143             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1144             output: &::I16x4,
1145             definition: Named("llvm.arm.neon.vqrshrns.v4i16")
1146         },
1147         "qrshrn_n_u32" => Intrinsic {
1148             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1149             output: &::U16x4,
1150             definition: Named("llvm.arm.neon.vqrshrnu.v4i16")
1151         },
1152         "qrshrn_n_s64" => Intrinsic {
1153             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1154             output: &::I32x2,
1155             definition: Named("llvm.arm.neon.vqrshrns.v2i32")
1156         },
1157         "qrshrn_n_u64" => Intrinsic {
1158             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1159             output: &::U32x2,
1160             definition: Named("llvm.arm.neon.vqrshrnu.v2i32")
1161         },
1162         "sri_s8" => Intrinsic {
1163             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1164             output: &::I8x8,
1165             definition: Named("llvm.arm.neon.vvsri.v8i8")
1166         },
1167         "sri_u8" => Intrinsic {
1168             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1169             output: &::U8x8,
1170             definition: Named("llvm.arm.neon.vvsri.v8i8")
1171         },
1172         "sri_s16" => Intrinsic {
1173             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1174             output: &::I16x4,
1175             definition: Named("llvm.arm.neon.vvsri.v4i16")
1176         },
1177         "sri_u16" => Intrinsic {
1178             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1179             output: &::U16x4,
1180             definition: Named("llvm.arm.neon.vvsri.v4i16")
1181         },
1182         "sri_s32" => Intrinsic {
1183             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1184             output: &::I32x2,
1185             definition: Named("llvm.arm.neon.vvsri.v2i32")
1186         },
1187         "sri_u32" => Intrinsic {
1188             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1189             output: &::U32x2,
1190             definition: Named("llvm.arm.neon.vvsri.v2i32")
1191         },
1192         "sri_s64" => Intrinsic {
1193             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1194             output: &::I64x1,
1195             definition: Named("llvm.arm.neon.vvsri.v1i64")
1196         },
1197         "sri_u64" => Intrinsic {
1198             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1199             output: &::U64x1,
1200             definition: Named("llvm.arm.neon.vvsri.v1i64")
1201         },
1202         "sriq_s8" => Intrinsic {
1203             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1204             output: &::I8x16,
1205             definition: Named("llvm.arm.neon.vvsri.v16i8")
1206         },
1207         "sriq_u8" => Intrinsic {
1208             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1209             output: &::U8x16,
1210             definition: Named("llvm.arm.neon.vvsri.v16i8")
1211         },
1212         "sriq_s16" => Intrinsic {
1213             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1214             output: &::I16x8,
1215             definition: Named("llvm.arm.neon.vvsri.v8i16")
1216         },
1217         "sriq_u16" => Intrinsic {
1218             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1219             output: &::U16x8,
1220             definition: Named("llvm.arm.neon.vvsri.v8i16")
1221         },
1222         "sriq_s32" => Intrinsic {
1223             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1224             output: &::I32x4,
1225             definition: Named("llvm.arm.neon.vvsri.v4i32")
1226         },
1227         "sriq_u32" => Intrinsic {
1228             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1229             output: &::U32x4,
1230             definition: Named("llvm.arm.neon.vvsri.v4i32")
1231         },
1232         "sriq_s64" => Intrinsic {
1233             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1234             output: &::I64x2,
1235             definition: Named("llvm.arm.neon.vvsri.v2i64")
1236         },
1237         "sriq_u64" => Intrinsic {
1238             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1239             output: &::U64x2,
1240             definition: Named("llvm.arm.neon.vvsri.v2i64")
1241         },
1242         "sli_s8" => Intrinsic {
1243             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1244             output: &::I8x8,
1245             definition: Named("llvm.arm.neon.vvsli.v8i8")
1246         },
1247         "sli_u8" => Intrinsic {
1248             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1249             output: &::U8x8,
1250             definition: Named("llvm.arm.neon.vvsli.v8i8")
1251         },
1252         "sli_s16" => Intrinsic {
1253             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1254             output: &::I16x4,
1255             definition: Named("llvm.arm.neon.vvsli.v4i16")
1256         },
1257         "sli_u16" => Intrinsic {
1258             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1259             output: &::U16x4,
1260             definition: Named("llvm.arm.neon.vvsli.v4i16")
1261         },
1262         "sli_s32" => Intrinsic {
1263             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1264             output: &::I32x2,
1265             definition: Named("llvm.arm.neon.vvsli.v2i32")
1266         },
1267         "sli_u32" => Intrinsic {
1268             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1269             output: &::U32x2,
1270             definition: Named("llvm.arm.neon.vvsli.v2i32")
1271         },
1272         "sli_s64" => Intrinsic {
1273             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1274             output: &::I64x1,
1275             definition: Named("llvm.arm.neon.vvsli.v1i64")
1276         },
1277         "sli_u64" => Intrinsic {
1278             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1279             output: &::U64x1,
1280             definition: Named("llvm.arm.neon.vvsli.v1i64")
1281         },
1282         "sliq_s8" => Intrinsic {
1283             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1284             output: &::I8x16,
1285             definition: Named("llvm.arm.neon.vvsli.v16i8")
1286         },
1287         "sliq_u8" => Intrinsic {
1288             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1289             output: &::U8x16,
1290             definition: Named("llvm.arm.neon.vvsli.v16i8")
1291         },
1292         "sliq_s16" => Intrinsic {
1293             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1294             output: &::I16x8,
1295             definition: Named("llvm.arm.neon.vvsli.v8i16")
1296         },
1297         "sliq_u16" => Intrinsic {
1298             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1299             output: &::U16x8,
1300             definition: Named("llvm.arm.neon.vvsli.v8i16")
1301         },
1302         "sliq_s32" => Intrinsic {
1303             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1304             output: &::I32x4,
1305             definition: Named("llvm.arm.neon.vvsli.v4i32")
1306         },
1307         "sliq_u32" => Intrinsic {
1308             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1309             output: &::U32x4,
1310             definition: Named("llvm.arm.neon.vvsli.v4i32")
1311         },
1312         "sliq_s64" => Intrinsic {
1313             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1314             output: &::I64x2,
1315             definition: Named("llvm.arm.neon.vvsli.v2i64")
1316         },
1317         "sliq_u64" => Intrinsic {
1318             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1319             output: &::U64x2,
1320             definition: Named("llvm.arm.neon.vvsli.v2i64")
1321         },
1322         "vqmovn_s16" => Intrinsic {
1323             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1324             output: &::I8x8,
1325             definition: Named("llvm.arm.neon.vqxtns.v8i8")
1326         },
1327         "vqmovn_u16" => Intrinsic {
1328             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1329             output: &::U8x8,
1330             definition: Named("llvm.arm.neon.vqxtnu.v8i8")
1331         },
1332         "vqmovn_s32" => Intrinsic {
1333             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1334             output: &::I16x4,
1335             definition: Named("llvm.arm.neon.vqxtns.v4i16")
1336         },
1337         "vqmovn_u32" => Intrinsic {
1338             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1339             output: &::U16x4,
1340             definition: Named("llvm.arm.neon.vqxtnu.v4i16")
1341         },
1342         "vqmovn_s64" => Intrinsic {
1343             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1344             output: &::I32x2,
1345             definition: Named("llvm.arm.neon.vqxtns.v2i32")
1346         },
1347         "vqmovn_u64" => Intrinsic {
1348             inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
1349             output: &::U32x2,
1350             definition: Named("llvm.arm.neon.vqxtnu.v2i32")
1351         },
1352         "abs_s8" => Intrinsic {
1353             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1354             output: &::I8x8,
1355             definition: Named("llvm.arm.neon.vabs.v8i8")
1356         },
1357         "abs_s16" => Intrinsic {
1358             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1359             output: &::I16x4,
1360             definition: Named("llvm.arm.neon.vabs.v4i16")
1361         },
1362         "abs_s32" => Intrinsic {
1363             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1364             output: &::I32x2,
1365             definition: Named("llvm.arm.neon.vabs.v2i32")
1366         },
1367         "absq_s8" => Intrinsic {
1368             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1369             output: &::I8x16,
1370             definition: Named("llvm.arm.neon.vabs.v16i8")
1371         },
1372         "absq_s16" => Intrinsic {
1373             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1374             output: &::I16x8,
1375             definition: Named("llvm.arm.neon.vabs.v8i16")
1376         },
1377         "absq_s32" => Intrinsic {
1378             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1379             output: &::I32x4,
1380             definition: Named("llvm.arm.neon.vabs.v4i32")
1381         },
1382         "abs_f32" => Intrinsic {
1383             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1384             output: &::F32x2,
1385             definition: Named("llvm.fabs.v2f32")
1386         },
1387         "absq_f32" => Intrinsic {
1388             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1389             output: &::F32x4,
1390             definition: Named("llvm.fabs.v4f32")
1391         },
1392         "qabs_s8" => Intrinsic {
1393             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1394             output: &::I8x8,
1395             definition: Named("llvm.arm.neon.vsqabs.v8i8")
1396         },
1397         "qabs_s16" => Intrinsic {
1398             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1399             output: &::I16x4,
1400             definition: Named("llvm.arm.neon.vsqabs.v4i16")
1401         },
1402         "qabs_s32" => Intrinsic {
1403             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1404             output: &::I32x2,
1405             definition: Named("llvm.arm.neon.vsqabs.v2i32")
1406         },
1407         "qabsq_s8" => Intrinsic {
1408             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1409             output: &::I8x16,
1410             definition: Named("llvm.arm.neon.vsqabs.v16i8")
1411         },
1412         "qabsq_s16" => Intrinsic {
1413             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1414             output: &::I16x8,
1415             definition: Named("llvm.arm.neon.vsqabs.v8i16")
1416         },
1417         "qabsq_s32" => Intrinsic {
1418             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1419             output: &::I32x4,
1420             definition: Named("llvm.arm.neon.vsqabs.v4i32")
1421         },
1422         "qneg_s8" => Intrinsic {
1423             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1424             output: &::I8x8,
1425             definition: Named("llvm.arm.neon.vsqneg.v8i8")
1426         },
1427         "qneg_s16" => Intrinsic {
1428             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1429             output: &::I16x4,
1430             definition: Named("llvm.arm.neon.vsqneg.v4i16")
1431         },
1432         "qneg_s32" => Intrinsic {
1433             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1434             output: &::I32x2,
1435             definition: Named("llvm.arm.neon.vsqneg.v2i32")
1436         },
1437         "qnegq_s8" => Intrinsic {
1438             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1439             output: &::I8x16,
1440             definition: Named("llvm.arm.neon.vsqneg.v16i8")
1441         },
1442         "qnegq_s16" => Intrinsic {
1443             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1444             output: &::I16x8,
1445             definition: Named("llvm.arm.neon.vsqneg.v8i16")
1446         },
1447         "qnegq_s32" => Intrinsic {
1448             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1449             output: &::I32x4,
1450             definition: Named("llvm.arm.neon.vsqneg.v4i32")
1451         },
1452         "clz_s8" => Intrinsic {
1453             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1454             output: &::I8x8,
1455             definition: Named("llvm.ctlz.v8i8")
1456         },
1457         "clz_u8" => Intrinsic {
1458             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1459             output: &::U8x8,
1460             definition: Named("llvm.ctlz.v8i8")
1461         },
1462         "clz_s16" => Intrinsic {
1463             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1464             output: &::I16x4,
1465             definition: Named("llvm.ctlz.v4i16")
1466         },
1467         "clz_u16" => Intrinsic {
1468             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1469             output: &::U16x4,
1470             definition: Named("llvm.ctlz.v4i16")
1471         },
1472         "clz_s32" => Intrinsic {
1473             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1474             output: &::I32x2,
1475             definition: Named("llvm.ctlz.v2i32")
1476         },
1477         "clz_u32" => Intrinsic {
1478             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1479             output: &::U32x2,
1480             definition: Named("llvm.ctlz.v2i32")
1481         },
1482         "clzq_s8" => Intrinsic {
1483             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1484             output: &::I8x16,
1485             definition: Named("llvm.ctlz.v16i8")
1486         },
1487         "clzq_u8" => Intrinsic {
1488             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1489             output: &::U8x16,
1490             definition: Named("llvm.ctlz.v16i8")
1491         },
1492         "clzq_s16" => Intrinsic {
1493             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1494             output: &::I16x8,
1495             definition: Named("llvm.ctlz.v8i16")
1496         },
1497         "clzq_u16" => Intrinsic {
1498             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1499             output: &::U16x8,
1500             definition: Named("llvm.ctlz.v8i16")
1501         },
1502         "clzq_s32" => Intrinsic {
1503             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1504             output: &::I32x4,
1505             definition: Named("llvm.ctlz.v4i32")
1506         },
1507         "clzq_u32" => Intrinsic {
1508             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1509             output: &::U32x4,
1510             definition: Named("llvm.ctlz.v4i32")
1511         },
1512         "cls_s8" => Intrinsic {
1513             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1514             output: &::I8x8,
1515             definition: Named("llvm.arm.neon.vcls.v8i8")
1516         },
1517         "cls_u8" => Intrinsic {
1518             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1519             output: &::U8x8,
1520             definition: Named("llvm.arm.neon.vcls.v8i8")
1521         },
1522         "cls_s16" => Intrinsic {
1523             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1524             output: &::I16x4,
1525             definition: Named("llvm.arm.neon.vcls.v4i16")
1526         },
1527         "cls_u16" => Intrinsic {
1528             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1529             output: &::U16x4,
1530             definition: Named("llvm.arm.neon.vcls.v4i16")
1531         },
1532         "cls_s32" => Intrinsic {
1533             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1534             output: &::I32x2,
1535             definition: Named("llvm.arm.neon.vcls.v2i32")
1536         },
1537         "cls_u32" => Intrinsic {
1538             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1539             output: &::U32x2,
1540             definition: Named("llvm.arm.neon.vcls.v2i32")
1541         },
1542         "clsq_s8" => Intrinsic {
1543             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1544             output: &::I8x16,
1545             definition: Named("llvm.arm.neon.vcls.v16i8")
1546         },
1547         "clsq_u8" => Intrinsic {
1548             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1549             output: &::U8x16,
1550             definition: Named("llvm.arm.neon.vcls.v16i8")
1551         },
1552         "clsq_s16" => Intrinsic {
1553             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1554             output: &::I16x8,
1555             definition: Named("llvm.arm.neon.vcls.v8i16")
1556         },
1557         "clsq_u16" => Intrinsic {
1558             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1559             output: &::U16x8,
1560             definition: Named("llvm.arm.neon.vcls.v8i16")
1561         },
1562         "clsq_s32" => Intrinsic {
1563             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1564             output: &::I32x4,
1565             definition: Named("llvm.arm.neon.vcls.v4i32")
1566         },
1567         "clsq_u32" => Intrinsic {
1568             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1569             output: &::U32x4,
1570             definition: Named("llvm.arm.neon.vcls.v4i32")
1571         },
1572         "cnt_s8" => Intrinsic {
1573             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1574             output: &::I8x8,
1575             definition: Named("llvm.ctpop.v8i8")
1576         },
1577         "cnt_u8" => Intrinsic {
1578             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1579             output: &::U8x8,
1580             definition: Named("llvm.ctpop.v8i8")
1581         },
1582         "cntq_s8" => Intrinsic {
1583             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1584             output: &::I8x16,
1585             definition: Named("llvm.ctpop.v16i8")
1586         },
1587         "cntq_u8" => Intrinsic {
1588             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1589             output: &::U8x16,
1590             definition: Named("llvm.ctpop.v16i8")
1591         },
1592         "recpe_u32" => Intrinsic {
1593             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1594             output: &::U32x2,
1595             definition: Named("llvm.arm.neon.vrecpe.v2i32")
1596         },
1597         "recpe_f32" => Intrinsic {
1598             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1599             output: &::F32x2,
1600             definition: Named("llvm.arm.neon.vrecpe.v2f32")
1601         },
1602         "recpeq_u32" => Intrinsic {
1603             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1604             output: &::U32x4,
1605             definition: Named("llvm.arm.neon.vrecpe.v4i32")
1606         },
1607         "recpeq_f32" => Intrinsic {
1608             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1609             output: &::F32x4,
1610             definition: Named("llvm.arm.neon.vrecpe.v4f32")
1611         },
1612         "recps_f32" => Intrinsic {
1613             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1614             output: &::F32x2,
1615             definition: Named("llvm.arm.neon.vfrecps.v2f32")
1616         },
1617         "recpsq_f32" => Intrinsic {
1618             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1619             output: &::F32x4,
1620             definition: Named("llvm.arm.neon.vfrecps.v4f32")
1621         },
1622         "sqrt_f32" => Intrinsic {
1623             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1624             output: &::F32x2,
1625             definition: Named("llvm.sqrt.v2f32")
1626         },
1627         "sqrtq_f32" => Intrinsic {
1628             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1629             output: &::F32x4,
1630             definition: Named("llvm.sqrt.v4f32")
1631         },
1632         "rsqrte_u32" => Intrinsic {
1633             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1634             output: &::U32x2,
1635             definition: Named("llvm.arm.neon.vrsqrte.v2i32")
1636         },
1637         "rsqrte_f32" => Intrinsic {
1638             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1639             output: &::F32x2,
1640             definition: Named("llvm.arm.neon.vrsqrte.v2f32")
1641         },
1642         "rsqrteq_u32" => Intrinsic {
1643             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1644             output: &::U32x4,
1645             definition: Named("llvm.arm.neon.vrsqrte.v4i32")
1646         },
1647         "rsqrteq_f32" => Intrinsic {
1648             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1649             output: &::F32x4,
1650             definition: Named("llvm.arm.neon.vrsqrte.v4f32")
1651         },
1652         "rsqrts_f32" => Intrinsic {
1653             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1654             output: &::F32x2,
1655             definition: Named("llvm.arm.neon.vrsqrts.v2f32")
1656         },
1657         "rsqrtsq_f32" => Intrinsic {
1658             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1659             output: &::F32x4,
1660             definition: Named("llvm.arm.neon.vrsqrts.v4f32")
1661         },
1662         "bsl_s8" => Intrinsic {
1663             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1664             output: &::I8x8,
1665             definition: Named("llvm.arm.neon.vbsl.v8i8")
1666         },
1667         "bsl_u8" => Intrinsic {
1668             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1669             output: &::U8x8,
1670             definition: Named("llvm.arm.neon.vbsl.v8i8")
1671         },
1672         "bsl_s16" => Intrinsic {
1673             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1674             output: &::I16x4,
1675             definition: Named("llvm.arm.neon.vbsl.v4i16")
1676         },
1677         "bsl_u16" => Intrinsic {
1678             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1679             output: &::U16x4,
1680             definition: Named("llvm.arm.neon.vbsl.v4i16")
1681         },
1682         "bsl_s32" => Intrinsic {
1683             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1684             output: &::I32x2,
1685             definition: Named("llvm.arm.neon.vbsl.v2i32")
1686         },
1687         "bsl_u32" => Intrinsic {
1688             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1689             output: &::U32x2,
1690             definition: Named("llvm.arm.neon.vbsl.v2i32")
1691         },
1692         "bsl_s64" => Intrinsic {
1693             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1694             output: &::I64x1,
1695             definition: Named("llvm.arm.neon.vbsl.v1i64")
1696         },
1697         "bsl_u64" => Intrinsic {
1698             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1699             output: &::U64x1,
1700             definition: Named("llvm.arm.neon.vbsl.v1i64")
1701         },
1702         "bslq_s8" => Intrinsic {
1703             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1704             output: &::I8x16,
1705             definition: Named("llvm.arm.neon.vbsl.v16i8")
1706         },
1707         "bslq_u8" => Intrinsic {
1708             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1709             output: &::U8x16,
1710             definition: Named("llvm.arm.neon.vbsl.v16i8")
1711         },
1712         "bslq_s16" => Intrinsic {
1713             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1714             output: &::I16x8,
1715             definition: Named("llvm.arm.neon.vbsl.v8i16")
1716         },
1717         "bslq_u16" => Intrinsic {
1718             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1719             output: &::U16x8,
1720             definition: Named("llvm.arm.neon.vbsl.v8i16")
1721         },
1722         "bslq_s32" => Intrinsic {
1723             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1724             output: &::I32x4,
1725             definition: Named("llvm.arm.neon.vbsl.v4i32")
1726         },
1727         "bslq_u32" => Intrinsic {
1728             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1729             output: &::U32x4,
1730             definition: Named("llvm.arm.neon.vbsl.v4i32")
1731         },
1732         "bslq_s64" => Intrinsic {
1733             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1734             output: &::I64x2,
1735             definition: Named("llvm.arm.neon.vbsl.v2i64")
1736         },
1737         "bslq_u64" => Intrinsic {
1738             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1739             output: &::U64x2,
1740             definition: Named("llvm.arm.neon.vbsl.v2i64")
1741         },
1742         "padd_s8" => Intrinsic {
1743             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1744             output: &::I8x8,
1745             definition: Named("llvm.arm.neon.vpadd.v8i8")
1746         },
1747         "padd_u8" => Intrinsic {
1748             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1749             output: &::U8x8,
1750             definition: Named("llvm.arm.neon.vpadd.v8i8")
1751         },
1752         "padd_s16" => Intrinsic {
1753             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1754             output: &::I16x4,
1755             definition: Named("llvm.arm.neon.vpadd.v4i16")
1756         },
1757         "padd_u16" => Intrinsic {
1758             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1759             output: &::U16x4,
1760             definition: Named("llvm.arm.neon.vpadd.v4i16")
1761         },
1762         "padd_s32" => Intrinsic {
1763             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1764             output: &::I32x2,
1765             definition: Named("llvm.arm.neon.vpadd.v2i32")
1766         },
1767         "padd_u32" => Intrinsic {
1768             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1769             output: &::U32x2,
1770             definition: Named("llvm.arm.neon.vpadd.v2i32")
1771         },
1772         "padd_f32" => Intrinsic {
1773             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1774             output: &::F32x2,
1775             definition: Named("llvm.arm.neon.vpadd.v2f32")
1776         },
1777         "paddl_s16" => Intrinsic {
1778             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1779             output: &::I16x4,
1780             definition: Named("llvm.arm.neon.vpaddls.v4i16.v8i8")
1781         },
1782         "paddl_u16" => Intrinsic {
1783             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1784             output: &::U16x4,
1785             definition: Named("llvm.arm.neon.vpaddlu.v4i16.v8i8")
1786         },
1787         "paddl_s32" => Intrinsic {
1788             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1789             output: &::I32x2,
1790             definition: Named("llvm.arm.neon.vpaddls.v2i32.v4i16")
1791         },
1792         "paddl_u32" => Intrinsic {
1793             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1794             output: &::U32x2,
1795             definition: Named("llvm.arm.neon.vpaddlu.v2i32.v4i16")
1796         },
1797         "paddl_s64" => Intrinsic {
1798             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1799             output: &::I64x1,
1800             definition: Named("llvm.arm.neon.vpaddls.v1i64.v2i32")
1801         },
1802         "paddl_u64" => Intrinsic {
1803             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1804             output: &::U64x1,
1805             definition: Named("llvm.arm.neon.vpaddlu.v1i64.v2i32")
1806         },
1807         "paddlq_s16" => Intrinsic {
1808             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1809             output: &::I16x8,
1810             definition: Named("llvm.arm.neon.vpaddls.v8i16.v16i8")
1811         },
1812         "paddlq_u16" => Intrinsic {
1813             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1814             output: &::U16x8,
1815             definition: Named("llvm.arm.neon.vpaddlu.v8i16.v16i8")
1816         },
1817         "paddlq_s32" => Intrinsic {
1818             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1819             output: &::I32x4,
1820             definition: Named("llvm.arm.neon.vpaddls.v4i32.v8i16")
1821         },
1822         "paddlq_u32" => Intrinsic {
1823             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1824             output: &::U32x4,
1825             definition: Named("llvm.arm.neon.vpaddlu.v4i32.v8i16")
1826         },
1827         "paddlq_s64" => Intrinsic {
1828             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1829             output: &::I64x2,
1830             definition: Named("llvm.arm.neon.vpaddls.v2i64.v4i32")
1831         },
1832         "paddlq_u64" => Intrinsic {
1833             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1834             output: &::U64x2,
1835             definition: Named("llvm.arm.neon.vpaddlu.v2i64.v4i32")
1836         },
1837         "padal_s16" => Intrinsic {
1838             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I8x8]; &INPUTS },
1839             output: &::I16x4,
1840             definition: Named("llvm.arm.neon.vpadals.v4i16.v4i16")
1841         },
1842         "padal_u16" => Intrinsic {
1843             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U8x8]; &INPUTS },
1844             output: &::U16x4,
1845             definition: Named("llvm.arm.neon.vpadalu.v4i16.v4i16")
1846         },
1847         "padal_s32" => Intrinsic {
1848             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I16x4]; &INPUTS },
1849             output: &::I32x2,
1850             definition: Named("llvm.arm.neon.vpadals.v2i32.v2i32")
1851         },
1852         "padal_u32" => Intrinsic {
1853             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U16x4]; &INPUTS },
1854             output: &::U32x2,
1855             definition: Named("llvm.arm.neon.vpadalu.v2i32.v2i32")
1856         },
1857         "padal_s64" => Intrinsic {
1858             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I32x2]; &INPUTS },
1859             output: &::I64x1,
1860             definition: Named("llvm.arm.neon.vpadals.v1i64.v1i64")
1861         },
1862         "padal_u64" => Intrinsic {
1863             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U32x2]; &INPUTS },
1864             output: &::U64x1,
1865             definition: Named("llvm.arm.neon.vpadalu.v1i64.v1i64")
1866         },
1867         "padalq_s16" => Intrinsic {
1868             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I8x16]; &INPUTS },
1869             output: &::I16x8,
1870             definition: Named("llvm.arm.neon.vpadals.v8i16.v8i16")
1871         },
1872         "padalq_u16" => Intrinsic {
1873             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U8x16]; &INPUTS },
1874             output: &::U16x8,
1875             definition: Named("llvm.arm.neon.vpadalu.v8i16.v8i16")
1876         },
1877         "padalq_s32" => Intrinsic {
1878             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I16x8]; &INPUTS },
1879             output: &::I32x4,
1880             definition: Named("llvm.arm.neon.vpadals.v4i32.v4i32")
1881         },
1882         "padalq_u32" => Intrinsic {
1883             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U16x8]; &INPUTS },
1884             output: &::U32x4,
1885             definition: Named("llvm.arm.neon.vpadalu.v4i32.v4i32")
1886         },
1887         "padalq_s64" => Intrinsic {
1888             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I32x4]; &INPUTS },
1889             output: &::I64x2,
1890             definition: Named("llvm.arm.neon.vpadals.v2i64.v2i64")
1891         },
1892         "padalq_u64" => Intrinsic {
1893             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32x4]; &INPUTS },
1894             output: &::U64x2,
1895             definition: Named("llvm.arm.neon.vpadalu.v2i64.v2i64")
1896         },
1897         "pmax_s8" => Intrinsic {
1898             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1899             output: &::I8x8,
1900             definition: Named("llvm.arm.neon.vpmaxs.v8i8")
1901         },
1902         "pmax_u8" => Intrinsic {
1903             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1904             output: &::U8x8,
1905             definition: Named("llvm.arm.neon.vpmaxu.v8i8")
1906         },
1907         "pmax_s16" => Intrinsic {
1908             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1909             output: &::I16x4,
1910             definition: Named("llvm.arm.neon.vpmaxs.v4i16")
1911         },
1912         "pmax_u16" => Intrinsic {
1913             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1914             output: &::U16x4,
1915             definition: Named("llvm.arm.neon.vpmaxu.v4i16")
1916         },
1917         "pmax_s32" => Intrinsic {
1918             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1919             output: &::I32x2,
1920             definition: Named("llvm.arm.neon.vpmaxs.v2i32")
1921         },
1922         "pmax_u32" => Intrinsic {
1923             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1924             output: &::U32x2,
1925             definition: Named("llvm.arm.neon.vpmaxu.v2i32")
1926         },
1927         "pmax_f32" => Intrinsic {
1928             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1929             output: &::F32x2,
1930             definition: Named("llvm.arm.neon.vpmaxf.v2f32")
1931         },
1932         "pmin_s8" => Intrinsic {
1933             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1934             output: &::I8x8,
1935             definition: Named("llvm.arm.neon.vpmins.v8i8")
1936         },
1937         "pmin_u8" => Intrinsic {
1938             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1939             output: &::U8x8,
1940             definition: Named("llvm.arm.neon.vpminu.v8i8")
1941         },
1942         "pmin_s16" => Intrinsic {
1943             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1944             output: &::I16x4,
1945             definition: Named("llvm.arm.neon.vpmins.v4i16")
1946         },
1947         "pmin_u16" => Intrinsic {
1948             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1949             output: &::U16x4,
1950             definition: Named("llvm.arm.neon.vpminu.v4i16")
1951         },
1952         "pmin_s32" => Intrinsic {
1953             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1954             output: &::I32x2,
1955             definition: Named("llvm.arm.neon.vpmins.v2i32")
1956         },
1957         "pmin_u32" => Intrinsic {
1958             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1959             output: &::U32x2,
1960             definition: Named("llvm.arm.neon.vpminu.v2i32")
1961         },
1962         "pmin_f32" => Intrinsic {
1963             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1964             output: &::F32x2,
1965             definition: Named("llvm.arm.neon.vpminf.v2f32")
1966         },
1967         "pminq_s8" => Intrinsic {
1968             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1969             output: &::I8x16,
1970             definition: Named("llvm.arm.neon.vpmins.v16i8")
1971         },
1972         "pminq_u8" => Intrinsic {
1973             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1974             output: &::U8x16,
1975             definition: Named("llvm.arm.neon.vpminu.v16i8")
1976         },
1977         "pminq_s16" => Intrinsic {
1978             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1979             output: &::I16x8,
1980             definition: Named("llvm.arm.neon.vpmins.v8i16")
1981         },
1982         "pminq_u16" => Intrinsic {
1983             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1984             output: &::U16x8,
1985             definition: Named("llvm.arm.neon.vpminu.v8i16")
1986         },
1987         "pminq_s32" => Intrinsic {
1988             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1989             output: &::I32x4,
1990             definition: Named("llvm.arm.neon.vpmins.v4i32")
1991         },
1992         "pminq_u32" => Intrinsic {
1993             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1994             output: &::U32x4,
1995             definition: Named("llvm.arm.neon.vpminu.v4i32")
1996         },
1997         "pminq_f32" => Intrinsic {
1998             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1999             output: &::F32x4,
2000             definition: Named("llvm.arm.neon.vpminf.v4f32")
2001         },
2002         "tbl1_s8" => Intrinsic {
2003             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::U8x8]; &INPUTS },
2004             output: &::I8x8,
2005             definition: Named("llvm.arm.neon.vtbl1")
2006         },
2007         "tbl1_u8" => Intrinsic {
2008             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2009             output: &::U8x8,
2010             definition: Named("llvm.arm.neon.vtbl1")
2011         },
2012         "tbx1_s8" => Intrinsic {
2013             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::U8x8]; &INPUTS },
2014             output: &::I8x8,
2015             definition: Named("llvm.arm.neon.vtbx1")
2016         },
2017         "tbx1_u8" => Intrinsic {
2018             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &INPUTS },
2019             output: &::U8x8,
2020             definition: Named("llvm.arm.neon.vtbx1")
2021         },
2022         "tbl2_s8" => Intrinsic {
2023             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2024             output: &::I8x8,
2025             definition: Named("llvm.arm.neon.vtbl2")
2026         },
2027         "tbl2_u8" => Intrinsic {
2028             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2029             output: &::U8x8,
2030             definition: Named("llvm.arm.neon.vtbl2")
2031         },
2032         "tbx2_s8" => Intrinsic {
2033             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2034             output: &::I8x8,
2035             definition: Named("llvm.arm.neon.vtbx2")
2036         },
2037         "tbx2_u8" => Intrinsic {
2038             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2039             output: &::U8x8,
2040             definition: Named("llvm.arm.neon.vtbx2")
2041         },
2042         "tbl3_s8" => Intrinsic {
2043             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2044             output: &::I8x8,
2045             definition: Named("llvm.arm.neon.vtbl3")
2046         },
2047         "tbl3_u8" => Intrinsic {
2048             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2049             output: &::U8x8,
2050             definition: Named("llvm.arm.neon.vtbl3")
2051         },
2052         "tbx3_s8" => Intrinsic {
2053             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2054             output: &::I8x8,
2055             definition: Named("llvm.arm.neon.vtbx3")
2056         },
2057         "tbx3_u8" => Intrinsic {
2058             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2059             output: &::U8x8,
2060             definition: Named("llvm.arm.neon.vtbx3")
2061         },
2062         "tbl4_s8" => Intrinsic {
2063             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2064             output: &::I8x8,
2065             definition: Named("llvm.arm.neon.vtbl4")
2066         },
2067         "tbl4_u8" => Intrinsic {
2068             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2069             output: &::U8x8,
2070             definition: Named("llvm.arm.neon.vtbl4")
2071         },
2072         "tbx4_s8" => Intrinsic {
2073             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2074             output: &::I8x8,
2075             definition: Named("llvm.arm.neon.vtbx4")
2076         },
2077         "tbx4_u8" => Intrinsic {
2078             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2079             output: &::U8x8,
2080             definition: Named("llvm.arm.neon.vtbx4")
2081         },
2082         _ => return None,
2083     })
2084 }