1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
2 // file at the top-level directory of this distribution and at
3 // http://rust-lang.org/COPYRIGHT.
5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
8 // option. This file may not be copied, modified, or distributed
9 // except according to those terms.
11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
12 // ignore-tidy-linelength
14 #![allow(unused_imports)]
16 use {Intrinsic, Type};
17 use IntrinsicDef::Named;
19 pub fn find(name: &str) -> Option<Intrinsic> {
20 if !name.starts_with("aarch64_v") { return None }
21 Some(match &name["aarch64_v".len()..] {
22 "hadd_s8" => Intrinsic {
23 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
25 definition: Named("llvm.aarch64.neon.shadd.v8i8")
27 "hadd_u8" => Intrinsic {
28 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
30 definition: Named("llvm.aarch64.neon.uhadd.v8i8")
32 "hadd_s16" => Intrinsic {
33 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
35 definition: Named("llvm.aarch64.neon.shadd.v4i16")
37 "hadd_u16" => Intrinsic {
38 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
40 definition: Named("llvm.aarch64.neon.uhadd.v4i16")
42 "hadd_s32" => Intrinsic {
43 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
45 definition: Named("llvm.aarch64.neon.shadd.v2i32")
47 "hadd_u32" => Intrinsic {
48 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
50 definition: Named("llvm.aarch64.neon.uhadd.v2i32")
52 "haddq_s8" => Intrinsic {
53 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
55 definition: Named("llvm.aarch64.neon.shadd.v16i8")
57 "haddq_u8" => Intrinsic {
58 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
60 definition: Named("llvm.aarch64.neon.uhadd.v16i8")
62 "haddq_s16" => Intrinsic {
63 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
65 definition: Named("llvm.aarch64.neon.shadd.v8i16")
67 "haddq_u16" => Intrinsic {
68 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
70 definition: Named("llvm.aarch64.neon.uhadd.v8i16")
72 "haddq_s32" => Intrinsic {
73 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
75 definition: Named("llvm.aarch64.neon.shadd.v4i32")
77 "haddq_u32" => Intrinsic {
78 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
80 definition: Named("llvm.aarch64.neon.uhadd.v4i32")
82 "rhadd_s8" => Intrinsic {
83 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
85 definition: Named("llvm.aarch64.neon.srhadd.v8i8")
87 "rhadd_u8" => Intrinsic {
88 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
90 definition: Named("llvm.aarch64.neon.urhadd.v8i8")
92 "rhadd_s16" => Intrinsic {
93 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
95 definition: Named("llvm.aarch64.neon.srhadd.v4i16")
97 "rhadd_u16" => Intrinsic {
98 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
100 definition: Named("llvm.aarch64.neon.urhadd.v4i16")
102 "rhadd_s32" => Intrinsic {
103 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
105 definition: Named("llvm.aarch64.neon.srhadd.v2i32")
107 "rhadd_u32" => Intrinsic {
108 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
110 definition: Named("llvm.aarch64.neon.urhadd.v2i32")
112 "rhaddq_s8" => Intrinsic {
113 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
115 definition: Named("llvm.aarch64.neon.srhadd.v16i8")
117 "rhaddq_u8" => Intrinsic {
118 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
120 definition: Named("llvm.aarch64.neon.urhadd.v16i8")
122 "rhaddq_s16" => Intrinsic {
123 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
125 definition: Named("llvm.aarch64.neon.srhadd.v8i16")
127 "rhaddq_u16" => Intrinsic {
128 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
130 definition: Named("llvm.aarch64.neon.urhadd.v8i16")
132 "rhaddq_s32" => Intrinsic {
133 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
135 definition: Named("llvm.aarch64.neon.srhadd.v4i32")
137 "rhaddq_u32" => Intrinsic {
138 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
140 definition: Named("llvm.aarch64.neon.urhadd.v4i32")
142 "qadd_s8" => Intrinsic {
143 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
145 definition: Named("llvm.aarch64.neon.sqadd.v8i8")
147 "qadd_u8" => Intrinsic {
148 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
150 definition: Named("llvm.aarch64.neon.uqadd.v8i8")
152 "qadd_s16" => Intrinsic {
153 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
155 definition: Named("llvm.aarch64.neon.sqadd.v4i16")
157 "qadd_u16" => Intrinsic {
158 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
160 definition: Named("llvm.aarch64.neon.uqadd.v4i16")
162 "qadd_s32" => Intrinsic {
163 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
165 definition: Named("llvm.aarch64.neon.sqadd.v2i32")
167 "qadd_u32" => Intrinsic {
168 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
170 definition: Named("llvm.aarch64.neon.uqadd.v2i32")
172 "qadd_s64" => Intrinsic {
173 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
175 definition: Named("llvm.aarch64.neon.sqadd.v1i64")
177 "qadd_u64" => Intrinsic {
178 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
180 definition: Named("llvm.aarch64.neon.uqadd.v1i64")
182 "qaddq_s8" => Intrinsic {
183 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
185 definition: Named("llvm.aarch64.neon.sqadd.v16i8")
187 "qaddq_u8" => Intrinsic {
188 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
190 definition: Named("llvm.aarch64.neon.uqadd.v16i8")
192 "qaddq_s16" => Intrinsic {
193 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
195 definition: Named("llvm.aarch64.neon.sqadd.v8i16")
197 "qaddq_u16" => Intrinsic {
198 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
200 definition: Named("llvm.aarch64.neon.uqadd.v8i16")
202 "qaddq_s32" => Intrinsic {
203 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
205 definition: Named("llvm.aarch64.neon.sqadd.v4i32")
207 "qaddq_u32" => Intrinsic {
208 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
210 definition: Named("llvm.aarch64.neon.uqadd.v4i32")
212 "qaddq_s64" => Intrinsic {
213 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
215 definition: Named("llvm.aarch64.neon.sqadd.v2i64")
217 "qaddq_u64" => Intrinsic {
218 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
220 definition: Named("llvm.aarch64.neon.uqadd.v2i64")
222 "uqadd_s8" => Intrinsic {
223 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS },
225 definition: Named("llvm.aarch64.neon.suqadd.v16i8")
227 "uqadd_s16" => Intrinsic {
228 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U16x8]; &INPUTS },
230 definition: Named("llvm.aarch64.neon.suqadd.v8i16")
232 "uqadd_s32" => Intrinsic {
233 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32x4]; &INPUTS },
235 definition: Named("llvm.aarch64.neon.suqadd.v4i32")
237 "uqadd_s64" => Intrinsic {
238 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U64x2]; &INPUTS },
240 definition: Named("llvm.aarch64.neon.suqadd.v2i64")
242 "sqadd_u8" => Intrinsic {
243 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
245 definition: Named("llvm.aarch64.neon.usqadd.v16i8")
247 "sqadd_u16" => Intrinsic {
248 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
250 definition: Named("llvm.aarch64.neon.usqadd.v8i16")
252 "sqadd_u32" => Intrinsic {
253 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
255 definition: Named("llvm.aarch64.neon.usqadd.v4i32")
257 "sqadd_u64" => Intrinsic {
258 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
260 definition: Named("llvm.aarch64.neon.usqadd.v2i64")
262 "raddhn_s16" => Intrinsic {
263 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
265 definition: Named("llvm.aarch64.neon.raddhn.v8i8")
267 "raddhn_u16" => Intrinsic {
268 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
270 definition: Named("llvm.aarch64.neon.raddhn.v8i8")
272 "raddhn_s32" => Intrinsic {
273 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
275 definition: Named("llvm.aarch64.neon.raddhn.v4i16")
277 "raddhn_u32" => Intrinsic {
278 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
280 definition: Named("llvm.aarch64.neon.raddhn.v4i16")
282 "raddhn_s64" => Intrinsic {
283 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
285 definition: Named("llvm.aarch64.neon.raddhn.v2i32")
287 "raddhn_u64" => Intrinsic {
288 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
290 definition: Named("llvm.aarch64.neon.raddhn.v2i32")
292 "fmulx_f32" => Intrinsic {
293 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
295 definition: Named("llvm.aarch64.neon.fmulx.v2f32")
297 "fmulx_f64" => Intrinsic {
298 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
300 definition: Named("llvm.aarch64.neon.fmulx.v1f64")
302 "fmulxq_f32" => Intrinsic {
303 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
305 definition: Named("llvm.aarch64.neon.fmulx.v4f32")
307 "fmulxq_f64" => Intrinsic {
308 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
310 definition: Named("llvm.aarch64.neon.fmulx.v2f64")
312 "fma_f32" => Intrinsic {
313 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
315 definition: Named("llvm.fma.v2f32")
317 "fma_f64" => Intrinsic {
318 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
320 definition: Named("llvm.fma.v1f64")
322 "fmaq_f32" => Intrinsic {
323 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
325 definition: Named("llvm.fma.v4f32")
327 "fmaq_f64" => Intrinsic {
328 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
330 definition: Named("llvm.fma.v2f64")
332 "qdmulh_s16" => Intrinsic {
333 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
335 definition: Named("llvm.aarch64.neon.sqdmulh.v4i16")
337 "qdmulh_s32" => Intrinsic {
338 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
340 definition: Named("llvm.aarch64.neon.sqdmulh.v2i32")
342 "qdmulhq_s16" => Intrinsic {
343 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
345 definition: Named("llvm.aarch64.neon.sqdmulh.v8i16")
347 "qdmulhq_s32" => Intrinsic {
348 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
350 definition: Named("llvm.aarch64.neon.sqdmulh.v4i32")
352 "qrdmulh_s16" => Intrinsic {
353 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
355 definition: Named("llvm.aarch64.neon.sqrdmulh.v4i16")
357 "qrdmulh_s32" => Intrinsic {
358 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
360 definition: Named("llvm.aarch64.neon.sqrdmulh.v2i32")
362 "qrdmulhq_s16" => Intrinsic {
363 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
365 definition: Named("llvm.aarch64.neon.sqrdmulh.v8i16")
367 "qrdmulhq_s32" => Intrinsic {
368 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
370 definition: Named("llvm.aarch64.neon.sqrdmulh.v4i32")
372 "mull_s8" => Intrinsic {
373 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
375 definition: Named("llvm.aarch64.neon.smull.v8i16")
377 "mull_u8" => Intrinsic {
378 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
380 definition: Named("llvm.aarch64.neon.umull.v8i16")
382 "mull_s16" => Intrinsic {
383 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
385 definition: Named("llvm.aarch64.neon.smull.v4i32")
387 "mull_u16" => Intrinsic {
388 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
390 definition: Named("llvm.aarch64.neon.umull.v4i32")
392 "mull_s32" => Intrinsic {
393 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
395 definition: Named("llvm.aarch64.neon.smull.v2i64")
397 "mull_u32" => Intrinsic {
398 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
400 definition: Named("llvm.aarch64.neon.umull.v2i64")
402 "qdmullq_s8" => Intrinsic {
403 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
405 definition: Named("llvm.aarch64.neon.sqdmull.v8i16")
407 "qdmullq_s16" => Intrinsic {
408 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
410 definition: Named("llvm.aarch64.neon.sqdmull.v4i32")
412 "hsub_s8" => Intrinsic {
413 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
415 definition: Named("llvm.aarch64.neon.shsub.v8i8")
417 "hsub_u8" => Intrinsic {
418 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
420 definition: Named("llvm.aarch64.neon.uhsub.v8i8")
422 "hsub_s16" => Intrinsic {
423 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
425 definition: Named("llvm.aarch64.neon.shsub.v4i16")
427 "hsub_u16" => Intrinsic {
428 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
430 definition: Named("llvm.aarch64.neon.uhsub.v4i16")
432 "hsub_s32" => Intrinsic {
433 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
435 definition: Named("llvm.aarch64.neon.shsub.v2i32")
437 "hsub_u32" => Intrinsic {
438 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
440 definition: Named("llvm.aarch64.neon.uhsub.v2i32")
442 "hsubq_s8" => Intrinsic {
443 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
445 definition: Named("llvm.aarch64.neon.shsub.v16i8")
447 "hsubq_u8" => Intrinsic {
448 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
450 definition: Named("llvm.aarch64.neon.uhsub.v16i8")
452 "hsubq_s16" => Intrinsic {
453 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
455 definition: Named("llvm.aarch64.neon.shsub.v8i16")
457 "hsubq_u16" => Intrinsic {
458 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
460 definition: Named("llvm.aarch64.neon.uhsub.v8i16")
462 "hsubq_s32" => Intrinsic {
463 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
465 definition: Named("llvm.aarch64.neon.shsub.v4i32")
467 "hsubq_u32" => Intrinsic {
468 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
470 definition: Named("llvm.aarch64.neon.uhsub.v4i32")
472 "qsub_s8" => Intrinsic {
473 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
475 definition: Named("llvm.aarch64.neon.sqsub.v8i8")
477 "qsub_u8" => Intrinsic {
478 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
480 definition: Named("llvm.aarch64.neon.uqsub.v8i8")
482 "qsub_s16" => Intrinsic {
483 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
485 definition: Named("llvm.aarch64.neon.sqsub.v4i16")
487 "qsub_u16" => Intrinsic {
488 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
490 definition: Named("llvm.aarch64.neon.uqsub.v4i16")
492 "qsub_s32" => Intrinsic {
493 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
495 definition: Named("llvm.aarch64.neon.sqsub.v2i32")
497 "qsub_u32" => Intrinsic {
498 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
500 definition: Named("llvm.aarch64.neon.uqsub.v2i32")
502 "qsub_s64" => Intrinsic {
503 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
505 definition: Named("llvm.aarch64.neon.sqsub.v1i64")
507 "qsub_u64" => Intrinsic {
508 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
510 definition: Named("llvm.aarch64.neon.uqsub.v1i64")
512 "qsubq_s8" => Intrinsic {
513 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
515 definition: Named("llvm.aarch64.neon.sqsub.v16i8")
517 "qsubq_u8" => Intrinsic {
518 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
520 definition: Named("llvm.aarch64.neon.uqsub.v16i8")
522 "qsubq_s16" => Intrinsic {
523 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
525 definition: Named("llvm.aarch64.neon.sqsub.v8i16")
527 "qsubq_u16" => Intrinsic {
528 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
530 definition: Named("llvm.aarch64.neon.uqsub.v8i16")
532 "qsubq_s32" => Intrinsic {
533 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
535 definition: Named("llvm.aarch64.neon.sqsub.v4i32")
537 "qsubq_u32" => Intrinsic {
538 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
540 definition: Named("llvm.aarch64.neon.uqsub.v4i32")
542 "qsubq_s64" => Intrinsic {
543 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
545 definition: Named("llvm.aarch64.neon.sqsub.v2i64")
547 "qsubq_u64" => Intrinsic {
548 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
550 definition: Named("llvm.aarch64.neon.uqsub.v2i64")
552 "rsubhn_s16" => Intrinsic {
553 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
555 definition: Named("llvm.aarch64.neon.rsubhn.v8i8")
557 "rsubhn_u16" => Intrinsic {
558 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
560 definition: Named("llvm.aarch64.neon.rsubhn.v8i8")
562 "rsubhn_s32" => Intrinsic {
563 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
565 definition: Named("llvm.aarch64.neon.rsubhn.v4i16")
567 "rsubhn_u32" => Intrinsic {
568 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
570 definition: Named("llvm.aarch64.neon.rsubhn.v4i16")
572 "rsubhn_s64" => Intrinsic {
573 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
575 definition: Named("llvm.aarch64.neon.rsubhn.v2i32")
577 "rsubhn_u64" => Intrinsic {
578 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
580 definition: Named("llvm.aarch64.neon.rsubhn.v2i32")
582 "abd_s8" => Intrinsic {
583 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
585 definition: Named("llvm.aarch64.neon.sabd.v8i8")
587 "abd_u8" => Intrinsic {
588 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
590 definition: Named("llvm.aarch64.neon.uabd.v8i8")
592 "abd_s16" => Intrinsic {
593 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
595 definition: Named("llvm.aarch64.neon.sabd.v4i16")
597 "abd_u16" => Intrinsic {
598 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
600 definition: Named("llvm.aarch64.neon.uabd.v4i16")
602 "abd_s32" => Intrinsic {
603 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
605 definition: Named("llvm.aarch64.neon.sabd.v2i32")
607 "abd_u32" => Intrinsic {
608 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
610 definition: Named("llvm.aarch64.neon.uabd.v2i32")
612 "abd_f32" => Intrinsic {
613 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
615 definition: Named("llvm.aarch64.neon.fabd.v2f32")
617 "abd_f64" => Intrinsic {
618 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
620 definition: Named("llvm.aarch64.neon.fabd.v1f64")
622 "abdq_s8" => Intrinsic {
623 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
625 definition: Named("llvm.aarch64.neon.sabd.v16i8")
627 "abdq_u8" => Intrinsic {
628 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
630 definition: Named("llvm.aarch64.neon.uabd.v16i8")
632 "abdq_s16" => Intrinsic {
633 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
635 definition: Named("llvm.aarch64.neon.sabd.v8i16")
637 "abdq_u16" => Intrinsic {
638 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
640 definition: Named("llvm.aarch64.neon.uabd.v8i16")
642 "abdq_s32" => Intrinsic {
643 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
645 definition: Named("llvm.aarch64.neon.sabd.v4i32")
647 "abdq_u32" => Intrinsic {
648 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
650 definition: Named("llvm.aarch64.neon.uabd.v4i32")
652 "abdq_f32" => Intrinsic {
653 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
655 definition: Named("llvm.aarch64.neon.fabd.v4f32")
657 "abdq_f64" => Intrinsic {
658 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
660 definition: Named("llvm.aarch64.neon.fabd.v2f64")
662 "max_s8" => Intrinsic {
663 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
665 definition: Named("llvm.aarch64.neon.smax.v8i8")
667 "max_u8" => Intrinsic {
668 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
670 definition: Named("llvm.aarch64.neon.umax.v8i8")
672 "max_s16" => Intrinsic {
673 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
675 definition: Named("llvm.aarch64.neon.smax.v4i16")
677 "max_u16" => Intrinsic {
678 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
680 definition: Named("llvm.aarch64.neon.umax.v4i16")
682 "max_s32" => Intrinsic {
683 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
685 definition: Named("llvm.aarch64.neon.smax.v2i32")
687 "max_u32" => Intrinsic {
688 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
690 definition: Named("llvm.aarch64.neon.umax.v2i32")
692 "max_f32" => Intrinsic {
693 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
695 definition: Named("llvm.aarch64.neon.fmax.v2f32")
697 "max_f64" => Intrinsic {
698 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
700 definition: Named("llvm.aarch64.neon.fmax.v1f64")
702 "maxq_s8" => Intrinsic {
703 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
705 definition: Named("llvm.aarch64.neon.smax.v16i8")
707 "maxq_u8" => Intrinsic {
708 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
710 definition: Named("llvm.aarch64.neon.umax.v16i8")
712 "maxq_s16" => Intrinsic {
713 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
715 definition: Named("llvm.aarch64.neon.smax.v8i16")
717 "maxq_u16" => Intrinsic {
718 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
720 definition: Named("llvm.aarch64.neon.umax.v8i16")
722 "maxq_s32" => Intrinsic {
723 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
725 definition: Named("llvm.aarch64.neon.smax.v4i32")
727 "maxq_u32" => Intrinsic {
728 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
730 definition: Named("llvm.aarch64.neon.umax.v4i32")
732 "maxq_f32" => Intrinsic {
733 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
735 definition: Named("llvm.aarch64.neon.fmax.v4f32")
737 "maxq_f64" => Intrinsic {
738 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
740 definition: Named("llvm.aarch64.neon.fmax.v2f64")
742 "min_s8" => Intrinsic {
743 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
745 definition: Named("llvm.aarch64.neon.smin.v8i8")
747 "min_u8" => Intrinsic {
748 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
750 definition: Named("llvm.aarch64.neon.umin.v8i8")
752 "min_s16" => Intrinsic {
753 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
755 definition: Named("llvm.aarch64.neon.smin.v4i16")
757 "min_u16" => Intrinsic {
758 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
760 definition: Named("llvm.aarch64.neon.umin.v4i16")
762 "min_s32" => Intrinsic {
763 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
765 definition: Named("llvm.aarch64.neon.smin.v2i32")
767 "min_u32" => Intrinsic {
768 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
770 definition: Named("llvm.aarch64.neon.umin.v2i32")
772 "min_f32" => Intrinsic {
773 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
775 definition: Named("llvm.aarch64.neon.fmin.v2f32")
777 "min_f64" => Intrinsic {
778 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
780 definition: Named("llvm.aarch64.neon.fmin.v1f64")
782 "minq_s8" => Intrinsic {
783 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
785 definition: Named("llvm.aarch64.neon.smin.v16i8")
787 "minq_u8" => Intrinsic {
788 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
790 definition: Named("llvm.aarch64.neon.umin.v16i8")
792 "minq_s16" => Intrinsic {
793 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
795 definition: Named("llvm.aarch64.neon.smin.v8i16")
797 "minq_u16" => Intrinsic {
798 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
800 definition: Named("llvm.aarch64.neon.umin.v8i16")
802 "minq_s32" => Intrinsic {
803 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
805 definition: Named("llvm.aarch64.neon.smin.v4i32")
807 "minq_u32" => Intrinsic {
808 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
810 definition: Named("llvm.aarch64.neon.umin.v4i32")
812 "minq_f32" => Intrinsic {
813 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
815 definition: Named("llvm.aarch64.neon.fmin.v4f32")
817 "minq_f64" => Intrinsic {
818 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
820 definition: Named("llvm.aarch64.neon.fmin.v2f64")
822 "maxnm_f32" => Intrinsic {
823 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
825 definition: Named("llvm.aarch64.neon.fmaxnm.v2f32")
827 "maxnm_f64" => Intrinsic {
828 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
830 definition: Named("llvm.aarch64.neon.fmaxnm.v1f64")
832 "maxnmq_f32" => Intrinsic {
833 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
835 definition: Named("llvm.aarch64.neon.fmaxnm.v4f32")
837 "maxnmq_f64" => Intrinsic {
838 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
840 definition: Named("llvm.aarch64.neon.fmaxnm.v2f64")
842 "minnm_f32" => Intrinsic {
843 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
845 definition: Named("llvm.aarch64.neon.fminnm.v2f32")
847 "minnm_f64" => Intrinsic {
848 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
850 definition: Named("llvm.aarch64.neon.fminnm.v1f64")
852 "minnmq_f32" => Intrinsic {
853 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
855 definition: Named("llvm.aarch64.neon.fminnm.v4f32")
857 "minnmq_f64" => Intrinsic {
858 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
860 definition: Named("llvm.aarch64.neon.fminnm.v2f64")
862 "shl_s8" => Intrinsic {
863 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
865 definition: Named("llvm.aarch64.neon.sshl.v8i8")
867 "shl_u8" => Intrinsic {
868 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
870 definition: Named("llvm.aarch64.neon.ushl.v8i8")
872 "shl_s16" => Intrinsic {
873 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
875 definition: Named("llvm.aarch64.neon.sshl.v4i16")
877 "shl_u16" => Intrinsic {
878 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
880 definition: Named("llvm.aarch64.neon.ushl.v4i16")
882 "shl_s32" => Intrinsic {
883 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
885 definition: Named("llvm.aarch64.neon.sshl.v2i32")
887 "shl_u32" => Intrinsic {
888 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
890 definition: Named("llvm.aarch64.neon.ushl.v2i32")
892 "shl_s64" => Intrinsic {
893 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
895 definition: Named("llvm.aarch64.neon.sshl.v1i64")
897 "shl_u64" => Intrinsic {
898 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
900 definition: Named("llvm.aarch64.neon.ushl.v1i64")
902 "shlq_s8" => Intrinsic {
903 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
905 definition: Named("llvm.aarch64.neon.sshl.v16i8")
907 "shlq_u8" => Intrinsic {
908 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
910 definition: Named("llvm.aarch64.neon.ushl.v16i8")
912 "shlq_s16" => Intrinsic {
913 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
915 definition: Named("llvm.aarch64.neon.sshl.v8i16")
917 "shlq_u16" => Intrinsic {
918 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
920 definition: Named("llvm.aarch64.neon.ushl.v8i16")
922 "shlq_s32" => Intrinsic {
923 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
925 definition: Named("llvm.aarch64.neon.sshl.v4i32")
927 "shlq_u32" => Intrinsic {
928 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
930 definition: Named("llvm.aarch64.neon.ushl.v4i32")
932 "shlq_s64" => Intrinsic {
933 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
935 definition: Named("llvm.aarch64.neon.sshl.v2i64")
937 "shlq_u64" => Intrinsic {
938 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
940 definition: Named("llvm.aarch64.neon.ushl.v2i64")
942 "qshl_s8" => Intrinsic {
943 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
945 definition: Named("llvm.aarch64.neon.sqshl.v8i8")
947 "qshl_u8" => Intrinsic {
948 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
950 definition: Named("llvm.aarch64.neon.uqshl.v8i8")
952 "qshl_s16" => Intrinsic {
953 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
955 definition: Named("llvm.aarch64.neon.sqshl.v4i16")
957 "qshl_u16" => Intrinsic {
958 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
960 definition: Named("llvm.aarch64.neon.uqshl.v4i16")
962 "qshl_s32" => Intrinsic {
963 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
965 definition: Named("llvm.aarch64.neon.sqshl.v2i32")
967 "qshl_u32" => Intrinsic {
968 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
970 definition: Named("llvm.aarch64.neon.uqshl.v2i32")
972 "qshl_s64" => Intrinsic {
973 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
975 definition: Named("llvm.aarch64.neon.sqshl.v1i64")
977 "qshl_u64" => Intrinsic {
978 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
980 definition: Named("llvm.aarch64.neon.uqshl.v1i64")
982 "qshlq_s8" => Intrinsic {
983 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
985 definition: Named("llvm.aarch64.neon.sqshl.v16i8")
987 "qshlq_u8" => Intrinsic {
988 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
990 definition: Named("llvm.aarch64.neon.uqshl.v16i8")
992 "qshlq_s16" => Intrinsic {
993 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
995 definition: Named("llvm.aarch64.neon.sqshl.v8i16")
997 "qshlq_u16" => Intrinsic {
998 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1000 definition: Named("llvm.aarch64.neon.uqshl.v8i16")
1002 "qshlq_s32" => Intrinsic {
1003 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1005 definition: Named("llvm.aarch64.neon.sqshl.v4i32")
1007 "qshlq_u32" => Intrinsic {
1008 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1010 definition: Named("llvm.aarch64.neon.uqshl.v4i32")
1012 "qshlq_s64" => Intrinsic {
1013 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1015 definition: Named("llvm.aarch64.neon.sqshl.v2i64")
1017 "qshlq_u64" => Intrinsic {
1018 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1020 definition: Named("llvm.aarch64.neon.uqshl.v2i64")
1022 "rshl_s8" => Intrinsic {
1023 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1025 definition: Named("llvm.aarch64.neon.srshl.v8i8")
1027 "rshl_u8" => Intrinsic {
1028 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1030 definition: Named("llvm.aarch64.neon.urshl.v8i8")
1032 "rshl_s16" => Intrinsic {
1033 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1035 definition: Named("llvm.aarch64.neon.srshl.v4i16")
1037 "rshl_u16" => Intrinsic {
1038 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1040 definition: Named("llvm.aarch64.neon.urshl.v4i16")
1042 "rshl_s32" => Intrinsic {
1043 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1045 definition: Named("llvm.aarch64.neon.srshl.v2i32")
1047 "rshl_u32" => Intrinsic {
1048 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1050 definition: Named("llvm.aarch64.neon.urshl.v2i32")
1052 "rshl_s64" => Intrinsic {
1053 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1055 definition: Named("llvm.aarch64.neon.srshl.v1i64")
1057 "rshl_u64" => Intrinsic {
1058 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1060 definition: Named("llvm.aarch64.neon.urshl.v1i64")
1062 "rshlq_s8" => Intrinsic {
1063 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1065 definition: Named("llvm.aarch64.neon.srshl.v16i8")
1067 "rshlq_u8" => Intrinsic {
1068 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1070 definition: Named("llvm.aarch64.neon.urshl.v16i8")
1072 "rshlq_s16" => Intrinsic {
1073 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1075 definition: Named("llvm.aarch64.neon.srshl.v8i16")
1077 "rshlq_u16" => Intrinsic {
1078 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1080 definition: Named("llvm.aarch64.neon.urshl.v8i16")
1082 "rshlq_s32" => Intrinsic {
1083 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1085 definition: Named("llvm.aarch64.neon.srshl.v4i32")
1087 "rshlq_u32" => Intrinsic {
1088 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1090 definition: Named("llvm.aarch64.neon.urshl.v4i32")
1092 "rshlq_s64" => Intrinsic {
1093 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1095 definition: Named("llvm.aarch64.neon.srshl.v2i64")
1097 "rshlq_u64" => Intrinsic {
1098 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1100 definition: Named("llvm.aarch64.neon.urshl.v2i64")
1102 "qrshl_s8" => Intrinsic {
1103 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1105 definition: Named("llvm.aarch64.neon.sqrshl.v8i8")
1107 "qrshl_u8" => Intrinsic {
1108 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1110 definition: Named("llvm.aarch64.neon.uqrshl.v8i8")
1112 "qrshl_s16" => Intrinsic {
1113 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1115 definition: Named("llvm.aarch64.neon.sqrshl.v4i16")
1117 "qrshl_u16" => Intrinsic {
1118 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1120 definition: Named("llvm.aarch64.neon.uqrshl.v4i16")
1122 "qrshl_s32" => Intrinsic {
1123 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1125 definition: Named("llvm.aarch64.neon.sqrshl.v2i32")
1127 "qrshl_u32" => Intrinsic {
1128 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1130 definition: Named("llvm.aarch64.neon.uqrshl.v2i32")
1132 "qrshl_s64" => Intrinsic {
1133 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1135 definition: Named("llvm.aarch64.neon.sqrshl.v1i64")
1137 "qrshl_u64" => Intrinsic {
1138 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1140 definition: Named("llvm.aarch64.neon.uqrshl.v1i64")
1142 "qrshlq_s8" => Intrinsic {
1143 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1145 definition: Named("llvm.aarch64.neon.sqrshl.v16i8")
1147 "qrshlq_u8" => Intrinsic {
1148 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1150 definition: Named("llvm.aarch64.neon.uqrshl.v16i8")
1152 "qrshlq_s16" => Intrinsic {
1153 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1155 definition: Named("llvm.aarch64.neon.sqrshl.v8i16")
1157 "qrshlq_u16" => Intrinsic {
1158 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1160 definition: Named("llvm.aarch64.neon.uqrshl.v8i16")
1162 "qrshlq_s32" => Intrinsic {
1163 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1165 definition: Named("llvm.aarch64.neon.sqrshl.v4i32")
1167 "qrshlq_u32" => Intrinsic {
1168 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1170 definition: Named("llvm.aarch64.neon.uqrshl.v4i32")
1172 "qrshlq_s64" => Intrinsic {
1173 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1175 definition: Named("llvm.aarch64.neon.sqrshl.v2i64")
1177 "qrshlq_u64" => Intrinsic {
1178 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1180 definition: Named("llvm.aarch64.neon.uqrshl.v2i64")
1182 "qshrun_n_s16" => Intrinsic {
1183 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1185 definition: Named("llvm.aarch64.neon.sqshrun.v8i8")
1187 "qshrun_n_s32" => Intrinsic {
1188 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1190 definition: Named("llvm.aarch64.neon.sqshrun.v4i16")
1192 "qshrun_n_s64" => Intrinsic {
1193 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1195 definition: Named("llvm.aarch64.neon.sqshrun.v2i32")
1197 "qrshrun_n_s16" => Intrinsic {
1198 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1200 definition: Named("llvm.aarch64.neon.sqrshrun.v8i8")
1202 "qrshrun_n_s32" => Intrinsic {
1203 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1205 definition: Named("llvm.aarch64.neon.sqrshrun.v4i16")
1207 "qrshrun_n_s64" => Intrinsic {
1208 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1210 definition: Named("llvm.aarch64.neon.sqrshrun.v2i32")
1212 "qshrn_n_s16" => Intrinsic {
1213 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1215 definition: Named("llvm.aarch64.neon.sqshrn.v8i8")
1217 "qshrn_n_u16" => Intrinsic {
1218 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1220 definition: Named("llvm.aarch64.neon.uqshrn.v8i8")
1222 "qshrn_n_s32" => Intrinsic {
1223 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1225 definition: Named("llvm.aarch64.neon.sqshrn.v4i16")
1227 "qshrn_n_u32" => Intrinsic {
1228 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1230 definition: Named("llvm.aarch64.neon.uqshrn.v4i16")
1232 "qshrn_n_s64" => Intrinsic {
1233 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1235 definition: Named("llvm.aarch64.neon.sqshrn.v2i32")
1237 "qshrn_n_u64" => Intrinsic {
1238 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1240 definition: Named("llvm.aarch64.neon.uqshrn.v2i32")
1242 "rshrn_n_s16" => Intrinsic {
1243 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1245 definition: Named("llvm.aarch64.neon.rshrn.v8i8")
1247 "rshrn_n_u16" => Intrinsic {
1248 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1250 definition: Named("llvm.aarch64.neon.rshrn.v8i8")
1252 "rshrn_n_s32" => Intrinsic {
1253 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1255 definition: Named("llvm.aarch64.neon.rshrn.v4i16")
1257 "rshrn_n_u32" => Intrinsic {
1258 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1260 definition: Named("llvm.aarch64.neon.rshrn.v4i16")
1262 "rshrn_n_s64" => Intrinsic {
1263 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1265 definition: Named("llvm.aarch64.neon.rshrn.v2i32")
1267 "rshrn_n_u64" => Intrinsic {
1268 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1270 definition: Named("llvm.aarch64.neon.rshrn.v2i32")
1272 "qrshrn_n_s16" => Intrinsic {
1273 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1275 definition: Named("llvm.aarch64.neon.sqrshrn.v8i8")
1277 "qrshrn_n_u16" => Intrinsic {
1278 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1280 definition: Named("llvm.aarch64.neon.uqrshrn.v8i8")
1282 "qrshrn_n_s32" => Intrinsic {
1283 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1285 definition: Named("llvm.aarch64.neon.sqrshrn.v4i16")
1287 "qrshrn_n_u32" => Intrinsic {
1288 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1290 definition: Named("llvm.aarch64.neon.uqrshrn.v4i16")
1292 "qrshrn_n_s64" => Intrinsic {
1293 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1295 definition: Named("llvm.aarch64.neon.sqrshrn.v2i32")
1297 "qrshrn_n_u64" => Intrinsic {
1298 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1300 definition: Named("llvm.aarch64.neon.uqrshrn.v2i32")
1302 "sri_s8" => Intrinsic {
1303 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1305 definition: Named("llvm.aarch64.neon.vsri.v8i8")
1307 "sri_u8" => Intrinsic {
1308 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1310 definition: Named("llvm.aarch64.neon.vsri.v8i8")
1312 "sri_s16" => Intrinsic {
1313 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1315 definition: Named("llvm.aarch64.neon.vsri.v4i16")
1317 "sri_u16" => Intrinsic {
1318 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1320 definition: Named("llvm.aarch64.neon.vsri.v4i16")
1322 "sri_s32" => Intrinsic {
1323 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1325 definition: Named("llvm.aarch64.neon.vsri.v2i32")
1327 "sri_u32" => Intrinsic {
1328 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1330 definition: Named("llvm.aarch64.neon.vsri.v2i32")
1332 "sri_s64" => Intrinsic {
1333 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1335 definition: Named("llvm.aarch64.neon.vsri.v1i64")
1337 "sri_u64" => Intrinsic {
1338 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1340 definition: Named("llvm.aarch64.neon.vsri.v1i64")
1342 "sriq_s8" => Intrinsic {
1343 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1345 definition: Named("llvm.aarch64.neon.vsri.v16i8")
1347 "sriq_u8" => Intrinsic {
1348 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1350 definition: Named("llvm.aarch64.neon.vsri.v16i8")
1352 "sriq_s16" => Intrinsic {
1353 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1355 definition: Named("llvm.aarch64.neon.vsri.v8i16")
1357 "sriq_u16" => Intrinsic {
1358 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1360 definition: Named("llvm.aarch64.neon.vsri.v8i16")
1362 "sriq_s32" => Intrinsic {
1363 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1365 definition: Named("llvm.aarch64.neon.vsri.v4i32")
1367 "sriq_u32" => Intrinsic {
1368 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1370 definition: Named("llvm.aarch64.neon.vsri.v4i32")
1372 "sriq_s64" => Intrinsic {
1373 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1375 definition: Named("llvm.aarch64.neon.vsri.v2i64")
1377 "sriq_u64" => Intrinsic {
1378 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1380 definition: Named("llvm.aarch64.neon.vsri.v2i64")
1382 "sli_s8" => Intrinsic {
1383 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1385 definition: Named("llvm.aarch64.neon.vsli.v8i8")
1387 "sli_u8" => Intrinsic {
1388 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1390 definition: Named("llvm.aarch64.neon.vsli.v8i8")
1392 "sli_s16" => Intrinsic {
1393 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1395 definition: Named("llvm.aarch64.neon.vsli.v4i16")
1397 "sli_u16" => Intrinsic {
1398 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1400 definition: Named("llvm.aarch64.neon.vsli.v4i16")
1402 "sli_s32" => Intrinsic {
1403 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1405 definition: Named("llvm.aarch64.neon.vsli.v2i32")
1407 "sli_u32" => Intrinsic {
1408 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1410 definition: Named("llvm.aarch64.neon.vsli.v2i32")
1412 "sli_s64" => Intrinsic {
1413 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1415 definition: Named("llvm.aarch64.neon.vsli.v1i64")
1417 "sli_u64" => Intrinsic {
1418 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1420 definition: Named("llvm.aarch64.neon.vsli.v1i64")
1422 "sliq_s8" => Intrinsic {
1423 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1425 definition: Named("llvm.aarch64.neon.vsli.v16i8")
1427 "sliq_u8" => Intrinsic {
1428 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1430 definition: Named("llvm.aarch64.neon.vsli.v16i8")
1432 "sliq_s16" => Intrinsic {
1433 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1435 definition: Named("llvm.aarch64.neon.vsli.v8i16")
1437 "sliq_u16" => Intrinsic {
1438 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1440 definition: Named("llvm.aarch64.neon.vsli.v8i16")
1442 "sliq_s32" => Intrinsic {
1443 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1445 definition: Named("llvm.aarch64.neon.vsli.v4i32")
1447 "sliq_u32" => Intrinsic {
1448 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1450 definition: Named("llvm.aarch64.neon.vsli.v4i32")
1452 "sliq_s64" => Intrinsic {
1453 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1455 definition: Named("llvm.aarch64.neon.vsli.v2i64")
1457 "sliq_u64" => Intrinsic {
1458 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1460 definition: Named("llvm.aarch64.neon.vsli.v2i64")
1462 "vqmovn_s16" => Intrinsic {
1463 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1465 definition: Named("llvm.aarch64.neon.sqxtn.v8i8")
1467 "vqmovn_u16" => Intrinsic {
1468 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1470 definition: Named("llvm.aarch64.neon.uqxtn.v8i8")
1472 "vqmovn_s32" => Intrinsic {
1473 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1475 definition: Named("llvm.aarch64.neon.sqxtn.v4i16")
1477 "vqmovn_u32" => Intrinsic {
1478 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1480 definition: Named("llvm.aarch64.neon.uqxtn.v4i16")
1482 "vqmovn_s64" => Intrinsic {
1483 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1485 definition: Named("llvm.aarch64.neon.sqxtn.v2i32")
1487 "vqmovn_u64" => Intrinsic {
1488 inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
1490 definition: Named("llvm.aarch64.neon.uqxtn.v2i32")
1492 "abs_s8" => Intrinsic {
1493 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1495 definition: Named("llvm.aarch64.neon.abs.v8i8")
1497 "abs_s16" => Intrinsic {
1498 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1500 definition: Named("llvm.aarch64.neon.abs.v4i16")
1502 "abs_s32" => Intrinsic {
1503 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1505 definition: Named("llvm.aarch64.neon.abs.v2i32")
1507 "abs_s64" => Intrinsic {
1508 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1510 definition: Named("llvm.aarch64.neon.abs.v1i64")
1512 "absq_s8" => Intrinsic {
1513 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1515 definition: Named("llvm.aarch64.neon.abs.v16i8")
1517 "absq_s16" => Intrinsic {
1518 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1520 definition: Named("llvm.aarch64.neon.abs.v8i16")
1522 "absq_s32" => Intrinsic {
1523 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1525 definition: Named("llvm.aarch64.neon.abs.v4i32")
1527 "absq_s64" => Intrinsic {
1528 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1530 definition: Named("llvm.aarch64.neon.abs.v2i64")
1532 "abs_f32" => Intrinsic {
1533 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1535 definition: Named("llvm.fabs.v2f32")
1537 "abs_f64" => Intrinsic {
1538 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1540 definition: Named("llvm.fabs.v1f64")
1542 "absq_f32" => Intrinsic {
1543 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1545 definition: Named("llvm.fabs.v4f32")
1547 "absq_f64" => Intrinsic {
1548 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1550 definition: Named("llvm.fabs.v2f64")
1552 "qabs_s8" => Intrinsic {
1553 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1555 definition: Named("llvm.aarch64.neon.sqabs.v8i8")
1557 "qabs_s16" => Intrinsic {
1558 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1560 definition: Named("llvm.aarch64.neon.sqabs.v4i16")
1562 "qabs_s32" => Intrinsic {
1563 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1565 definition: Named("llvm.aarch64.neon.sqabs.v2i32")
1567 "qabs_s64" => Intrinsic {
1568 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1570 definition: Named("llvm.aarch64.neon.sqabs.v1i64")
1572 "qabsq_s8" => Intrinsic {
1573 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1575 definition: Named("llvm.aarch64.neon.sqabs.v16i8")
1577 "qabsq_s16" => Intrinsic {
1578 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1580 definition: Named("llvm.aarch64.neon.sqabs.v8i16")
1582 "qabsq_s32" => Intrinsic {
1583 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1585 definition: Named("llvm.aarch64.neon.sqabs.v4i32")
1587 "qabsq_s64" => Intrinsic {
1588 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1590 definition: Named("llvm.aarch64.neon.sqabs.v2i64")
1592 "qneg_s8" => Intrinsic {
1593 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1595 definition: Named("llvm.aarch64.neon.sqneg.v8i8")
1597 "qneg_s16" => Intrinsic {
1598 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1600 definition: Named("llvm.aarch64.neon.sqneg.v4i16")
1602 "qneg_s32" => Intrinsic {
1603 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1605 definition: Named("llvm.aarch64.neon.sqneg.v2i32")
1607 "qneg_s64" => Intrinsic {
1608 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1610 definition: Named("llvm.aarch64.neon.sqneg.v1i64")
1612 "qnegq_s8" => Intrinsic {
1613 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1615 definition: Named("llvm.aarch64.neon.sqneg.v16i8")
1617 "qnegq_s16" => Intrinsic {
1618 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1620 definition: Named("llvm.aarch64.neon.sqneg.v8i16")
1622 "qnegq_s32" => Intrinsic {
1623 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1625 definition: Named("llvm.aarch64.neon.sqneg.v4i32")
1627 "qnegq_s64" => Intrinsic {
1628 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1630 definition: Named("llvm.aarch64.neon.sqneg.v2i64")
1632 "clz_s8" => Intrinsic {
1633 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1635 definition: Named("llvm.ctlz.v8i8")
1637 "clz_u8" => Intrinsic {
1638 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1640 definition: Named("llvm.ctlz.v8i8")
1642 "clz_s16" => Intrinsic {
1643 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1645 definition: Named("llvm.ctlz.v4i16")
1647 "clz_u16" => Intrinsic {
1648 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1650 definition: Named("llvm.ctlz.v4i16")
1652 "clz_s32" => Intrinsic {
1653 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1655 definition: Named("llvm.ctlz.v2i32")
1657 "clz_u32" => Intrinsic {
1658 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1660 definition: Named("llvm.ctlz.v2i32")
1662 "clzq_s8" => Intrinsic {
1663 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1665 definition: Named("llvm.ctlz.v16i8")
1667 "clzq_u8" => Intrinsic {
1668 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1670 definition: Named("llvm.ctlz.v16i8")
1672 "clzq_s16" => Intrinsic {
1673 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1675 definition: Named("llvm.ctlz.v8i16")
1677 "clzq_u16" => Intrinsic {
1678 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1680 definition: Named("llvm.ctlz.v8i16")
1682 "clzq_s32" => Intrinsic {
1683 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1685 definition: Named("llvm.ctlz.v4i32")
1687 "clzq_u32" => Intrinsic {
1688 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1690 definition: Named("llvm.ctlz.v4i32")
1692 "cls_s8" => Intrinsic {
1693 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1695 definition: Named("llvm.aarch64.neon.cls.v8i8")
1697 "cls_u8" => Intrinsic {
1698 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1700 definition: Named("llvm.aarch64.neon.cls.v8i8")
1702 "cls_s16" => Intrinsic {
1703 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1705 definition: Named("llvm.aarch64.neon.cls.v4i16")
1707 "cls_u16" => Intrinsic {
1708 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1710 definition: Named("llvm.aarch64.neon.cls.v4i16")
1712 "cls_s32" => Intrinsic {
1713 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1715 definition: Named("llvm.aarch64.neon.cls.v2i32")
1717 "cls_u32" => Intrinsic {
1718 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1720 definition: Named("llvm.aarch64.neon.cls.v2i32")
1722 "clsq_s8" => Intrinsic {
1723 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1725 definition: Named("llvm.aarch64.neon.cls.v16i8")
1727 "clsq_u8" => Intrinsic {
1728 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1730 definition: Named("llvm.aarch64.neon.cls.v16i8")
1732 "clsq_s16" => Intrinsic {
1733 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1735 definition: Named("llvm.aarch64.neon.cls.v8i16")
1737 "clsq_u16" => Intrinsic {
1738 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1740 definition: Named("llvm.aarch64.neon.cls.v8i16")
1742 "clsq_s32" => Intrinsic {
1743 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1745 definition: Named("llvm.aarch64.neon.cls.v4i32")
1747 "clsq_u32" => Intrinsic {
1748 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1750 definition: Named("llvm.aarch64.neon.cls.v4i32")
1752 "cnt_s8" => Intrinsic {
1753 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1755 definition: Named("llvm.ctpop.v8i8")
1757 "cnt_u8" => Intrinsic {
1758 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1760 definition: Named("llvm.ctpop.v8i8")
1762 "cntq_s8" => Intrinsic {
1763 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1765 definition: Named("llvm.ctpop.v16i8")
1767 "cntq_u8" => Intrinsic {
1768 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1770 definition: Named("llvm.ctpop.v16i8")
1772 "recpe_u32" => Intrinsic {
1773 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1775 definition: Named("llvm.aarch64.neon.urecpe.v2i32")
1777 "recpe_f32" => Intrinsic {
1778 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1780 definition: Named("llvm.aarch64.neon.frecpe.v2f32")
1782 "recpe_f64" => Intrinsic {
1783 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1785 definition: Named("llvm.aarch64.neon.frecpe.v1f64")
1787 "recpeq_u32" => Intrinsic {
1788 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1790 definition: Named("llvm.aarch64.neon.urecpe.v4i32")
1792 "recpeq_f32" => Intrinsic {
1793 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1795 definition: Named("llvm.aarch64.neon.frecpe.v4f32")
1797 "recpeq_f64" => Intrinsic {
1798 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1800 definition: Named("llvm.aarch64.neon.frecpe.v2f64")
1802 "recps_f32" => Intrinsic {
1803 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1805 definition: Named("llvm.aarch64.neon.frecps.v2f32")
1807 "recps_f64" => Intrinsic {
1808 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
1810 definition: Named("llvm.aarch64.neon.frecps.v1f64")
1812 "recpsq_f32" => Intrinsic {
1813 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1815 definition: Named("llvm.aarch64.neon.frecps.v4f32")
1817 "recpsq_f64" => Intrinsic {
1818 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
1820 definition: Named("llvm.aarch64.neon.frecps.v2f64")
1822 "sqrt_f32" => Intrinsic {
1823 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1825 definition: Named("llvm.sqrt.v2f32")
1827 "sqrt_f64" => Intrinsic {
1828 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1830 definition: Named("llvm.sqrt.v1f64")
1832 "sqrtq_f32" => Intrinsic {
1833 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1835 definition: Named("llvm.sqrt.v4f32")
1837 "sqrtq_f64" => Intrinsic {
1838 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1840 definition: Named("llvm.sqrt.v2f64")
1842 "rsqrte_u32" => Intrinsic {
1843 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1845 definition: Named("llvm.aarch64.neon.ursqrte.v2i32")
1847 "rsqrte_f32" => Intrinsic {
1848 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1850 definition: Named("llvm.aarch64.neon.frsqrte.v2f32")
1852 "rsqrte_f64" => Intrinsic {
1853 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1855 definition: Named("llvm.aarch64.neon.frsqrte.v1f64")
1857 "rsqrteq_u32" => Intrinsic {
1858 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1860 definition: Named("llvm.aarch64.neon.ursqrte.v4i32")
1862 "rsqrteq_f32" => Intrinsic {
1863 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1865 definition: Named("llvm.aarch64.neon.frsqrte.v4f32")
1867 "rsqrteq_f64" => Intrinsic {
1868 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1870 definition: Named("llvm.aarch64.neon.frsqrte.v2f64")
1872 "rsqrts_f32" => Intrinsic {
1873 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1875 definition: Named("llvm.aarch64.neon.frsqrts.v2f32")
1877 "rsqrts_f64" => Intrinsic {
1878 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
1880 definition: Named("llvm.aarch64.neon.frsqrts.v1f64")
1882 "rsqrtsq_f32" => Intrinsic {
1883 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1885 definition: Named("llvm.aarch64.neon.frsqrts.v4f32")
1887 "rsqrtsq_f64" => Intrinsic {
1888 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
1890 definition: Named("llvm.aarch64.neon.frsqrts.v2f64")
1892 "rbit_s8" => Intrinsic {
1893 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1895 definition: Named("llvm.aarch64.neon.rbit.v8i8")
1897 "rbit_u8" => Intrinsic {
1898 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1900 definition: Named("llvm.aarch64.neon.rbit.v8i8")
1902 "rbitq_s8" => Intrinsic {
1903 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1905 definition: Named("llvm.aarch64.neon.rbit.v16i8")
1907 "rbitq_u8" => Intrinsic {
1908 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1910 definition: Named("llvm.aarch64.neon.rbit.v16i8")
1912 "ld2_s8" => Intrinsic {
1913 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
1914 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG },
1915 definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1917 "ld2_u8" => Intrinsic {
1918 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
1919 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG },
1920 definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1922 "ld2_s16" => Intrinsic {
1923 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
1924 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG },
1925 definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1927 "ld2_u16" => Intrinsic {
1928 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
1929 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG },
1930 definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1932 "ld2_s32" => Intrinsic {
1933 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
1934 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG },
1935 definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1937 "ld2_u32" => Intrinsic {
1938 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
1939 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG },
1940 definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1942 "ld2_s64" => Intrinsic {
1943 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
1944 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG },
1945 definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1947 "ld2_u64" => Intrinsic {
1948 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
1949 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG },
1950 definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1952 "ld2_f32" => Intrinsic {
1953 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
1954 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG },
1955 definition: Named("llvm.aarch64.neon.ld2.v2f32.p0v2f32")
1957 "ld2_f64" => Intrinsic {
1958 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
1959 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG },
1960 definition: Named("llvm.aarch64.neon.ld2.v1f64.p0v1f64")
1962 "ld2q_s8" => Intrinsic {
1963 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
1964 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG },
1965 definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1967 "ld2q_u8" => Intrinsic {
1968 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
1969 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG },
1970 definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1972 "ld2q_s16" => Intrinsic {
1973 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
1974 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG },
1975 definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1977 "ld2q_u16" => Intrinsic {
1978 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
1979 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG },
1980 definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1982 "ld2q_s32" => Intrinsic {
1983 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
1984 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG },
1985 definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1987 "ld2q_u32" => Intrinsic {
1988 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
1989 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG },
1990 definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1992 "ld2q_s64" => Intrinsic {
1993 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
1994 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG },
1995 definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
1997 "ld2q_u64" => Intrinsic {
1998 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
1999 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG },
2000 definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
2002 "ld2q_f32" => Intrinsic {
2003 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2004 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG },
2005 definition: Named("llvm.aarch64.neon.ld2.v4f32.p0v4f32")
2007 "ld2q_f64" => Intrinsic {
2008 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2009 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG },
2010 definition: Named("llvm.aarch64.neon.ld2.v2f64.p0v2f64")
2012 "ld3_s8" => Intrinsic {
2013 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
2014 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2015 definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2017 "ld3_u8" => Intrinsic {
2018 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
2019 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2020 definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2022 "ld3_s16" => Intrinsic {
2023 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
2024 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2025 definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2027 "ld3_u16" => Intrinsic {
2028 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
2029 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2030 definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2032 "ld3_s32" => Intrinsic {
2033 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
2034 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2035 definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2037 "ld3_u32" => Intrinsic {
2038 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
2039 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2040 definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2042 "ld3_s64" => Intrinsic {
2043 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
2044 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2045 definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2047 "ld3_u64" => Intrinsic {
2048 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
2049 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2050 definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2052 "ld3_f32" => Intrinsic {
2053 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
2054 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2055 definition: Named("llvm.aarch64.neon.ld3.v2f32.p0v2f32")
2057 "ld3_f64" => Intrinsic {
2058 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
2059 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2060 definition: Named("llvm.aarch64.neon.ld3.v1f64.p0v1f64")
2062 "ld3q_s8" => Intrinsic {
2063 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
2064 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2065 definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2067 "ld3q_u8" => Intrinsic {
2068 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
2069 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2070 definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2072 "ld3q_s16" => Intrinsic {
2073 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
2074 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2075 definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2077 "ld3q_u16" => Intrinsic {
2078 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
2079 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2080 definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2082 "ld3q_s32" => Intrinsic {
2083 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
2084 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2085 definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2087 "ld3q_u32" => Intrinsic {
2088 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
2089 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2090 definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2092 "ld3q_s64" => Intrinsic {
2093 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
2094 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2095 definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2097 "ld3q_u64" => Intrinsic {
2098 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
2099 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2100 definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2102 "ld3q_f32" => Intrinsic {
2103 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2104 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2105 definition: Named("llvm.aarch64.neon.ld3.v4f32.p0v4f32")
2107 "ld3q_f64" => Intrinsic {
2108 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2109 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2110 definition: Named("llvm.aarch64.neon.ld3.v2f64.p0v2f64")
2112 "ld4_s8" => Intrinsic {
2113 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
2114 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2115 definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2117 "ld4_u8" => Intrinsic {
2118 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
2119 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2120 definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2122 "ld4_s16" => Intrinsic {
2123 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
2124 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2125 definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2127 "ld4_u16" => Intrinsic {
2128 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
2129 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2130 definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2132 "ld4_s32" => Intrinsic {
2133 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
2134 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2135 definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2137 "ld4_u32" => Intrinsic {
2138 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
2139 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2140 definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2142 "ld4_s64" => Intrinsic {
2143 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
2144 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2145 definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2147 "ld4_u64" => Intrinsic {
2148 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
2149 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2150 definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2152 "ld4_f32" => Intrinsic {
2153 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
2154 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2155 definition: Named("llvm.aarch64.neon.ld4.v2f32.p0v2f32")
2157 "ld4_f64" => Intrinsic {
2158 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
2159 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2160 definition: Named("llvm.aarch64.neon.ld4.v1f64.p0v1f64")
2162 "ld4q_s8" => Intrinsic {
2163 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
2164 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2165 definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2167 "ld4q_u8" => Intrinsic {
2168 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
2169 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2170 definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2172 "ld4q_s16" => Intrinsic {
2173 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
2174 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2175 definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2177 "ld4q_u16" => Intrinsic {
2178 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
2179 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2180 definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2182 "ld4q_s32" => Intrinsic {
2183 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
2184 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2185 definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2187 "ld4q_u32" => Intrinsic {
2188 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
2189 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2190 definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2192 "ld4q_s64" => Intrinsic {
2193 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
2194 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2195 definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2197 "ld4q_u64" => Intrinsic {
2198 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
2199 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2200 definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2202 "ld4q_f32" => Intrinsic {
2203 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2204 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2205 definition: Named("llvm.aarch64.neon.ld4.v4f32.p0v4f32")
2207 "ld4q_f64" => Intrinsic {
2208 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2209 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2210 definition: Named("llvm.aarch64.neon.ld4.v2f64.p0v2f64")
2212 "ld2_dup_s8" => Intrinsic {
2213 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2214 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG },
2215 definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2217 "ld2_dup_u8" => Intrinsic {
2218 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2219 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG },
2220 definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2222 "ld2_dup_s16" => Intrinsic {
2223 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2224 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG },
2225 definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2227 "ld2_dup_u16" => Intrinsic {
2228 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2229 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG },
2230 definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2232 "ld2_dup_s32" => Intrinsic {
2233 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2234 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG },
2235 definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2237 "ld2_dup_u32" => Intrinsic {
2238 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2239 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG },
2240 definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2242 "ld2_dup_s64" => Intrinsic {
2243 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2244 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG },
2245 definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2247 "ld2_dup_u64" => Intrinsic {
2248 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2249 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG },
2250 definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2252 "ld2_dup_f32" => Intrinsic {
2253 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2254 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG },
2255 definition: Named("llvm.aarch64.neon.ld2.v2f32.p0f32")
2257 "ld2_dup_f64" => Intrinsic {
2258 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2259 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG },
2260 definition: Named("llvm.aarch64.neon.ld2.v1f64.p0f64")
2262 "ld2q_dup_s8" => Intrinsic {
2263 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2264 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG },
2265 definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2267 "ld2q_dup_u8" => Intrinsic {
2268 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2269 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG },
2270 definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2272 "ld2q_dup_s16" => Intrinsic {
2273 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2274 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG },
2275 definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2277 "ld2q_dup_u16" => Intrinsic {
2278 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2279 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG },
2280 definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2282 "ld2q_dup_s32" => Intrinsic {
2283 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2284 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG },
2285 definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2287 "ld2q_dup_u32" => Intrinsic {
2288 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2289 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG },
2290 definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2292 "ld2q_dup_s64" => Intrinsic {
2293 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2294 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG },
2295 definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2297 "ld2q_dup_u64" => Intrinsic {
2298 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2299 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG },
2300 definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2302 "ld2q_dup_f32" => Intrinsic {
2303 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2304 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG },
2305 definition: Named("llvm.aarch64.neon.ld2.v4f32.p0f32")
2307 "ld2q_dup_f64" => Intrinsic {
2308 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2309 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG },
2310 definition: Named("llvm.aarch64.neon.ld2.v2f64.p0f64")
2312 "ld3_dup_s8" => Intrinsic {
2313 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2314 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2315 definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2317 "ld3_dup_u8" => Intrinsic {
2318 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2319 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2320 definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2322 "ld3_dup_s16" => Intrinsic {
2323 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2324 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2325 definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2327 "ld3_dup_u16" => Intrinsic {
2328 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2329 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2330 definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2332 "ld3_dup_s32" => Intrinsic {
2333 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2334 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2335 definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2337 "ld3_dup_u32" => Intrinsic {
2338 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2339 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2340 definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2342 "ld3_dup_s64" => Intrinsic {
2343 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2344 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2345 definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2347 "ld3_dup_u64" => Intrinsic {
2348 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2349 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2350 definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2352 "ld3_dup_f32" => Intrinsic {
2353 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2354 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2355 definition: Named("llvm.aarch64.neon.ld3.v2f32.p0f32")
2357 "ld3_dup_f64" => Intrinsic {
2358 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2359 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2360 definition: Named("llvm.aarch64.neon.ld3.v1f64.p0f64")
2362 "ld3q_dup_s8" => Intrinsic {
2363 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2364 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2365 definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2367 "ld3q_dup_u8" => Intrinsic {
2368 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2369 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2370 definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2372 "ld3q_dup_s16" => Intrinsic {
2373 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2374 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2375 definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2377 "ld3q_dup_u16" => Intrinsic {
2378 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2379 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2380 definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2382 "ld3q_dup_s32" => Intrinsic {
2383 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2384 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2385 definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2387 "ld3q_dup_u32" => Intrinsic {
2388 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2389 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2390 definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2392 "ld3q_dup_s64" => Intrinsic {
2393 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2394 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2395 definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2397 "ld3q_dup_u64" => Intrinsic {
2398 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2399 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2400 definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2402 "ld3q_dup_f32" => Intrinsic {
2403 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2404 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2405 definition: Named("llvm.aarch64.neon.ld3.v4f32.p0f32")
2407 "ld3q_dup_f64" => Intrinsic {
2408 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2409 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2410 definition: Named("llvm.aarch64.neon.ld3.v2f64.p0f64")
2412 "ld4_dup_s8" => Intrinsic {
2413 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2414 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2415 definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2417 "ld4_dup_u8" => Intrinsic {
2418 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2419 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2420 definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2422 "ld4_dup_s16" => Intrinsic {
2423 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2424 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2425 definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2427 "ld4_dup_u16" => Intrinsic {
2428 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2429 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2430 definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2432 "ld4_dup_s32" => Intrinsic {
2433 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2434 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2435 definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2437 "ld4_dup_u32" => Intrinsic {
2438 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2439 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2440 definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2442 "ld4_dup_s64" => Intrinsic {
2443 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2444 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2445 definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2447 "ld4_dup_u64" => Intrinsic {
2448 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2449 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2450 definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2452 "ld4_dup_f32" => Intrinsic {
2453 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2454 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2455 definition: Named("llvm.aarch64.neon.ld4.v2f32.p0f32")
2457 "ld4_dup_f64" => Intrinsic {
2458 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2459 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2460 definition: Named("llvm.aarch64.neon.ld4.v1f64.p0f64")
2462 "ld4q_dup_s8" => Intrinsic {
2463 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2464 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2465 definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2467 "ld4q_dup_u8" => Intrinsic {
2468 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2469 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2470 definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2472 "ld4q_dup_s16" => Intrinsic {
2473 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2474 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2475 definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2477 "ld4q_dup_u16" => Intrinsic {
2478 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2479 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2480 definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2482 "ld4q_dup_s32" => Intrinsic {
2483 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2484 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2485 definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2487 "ld4q_dup_u32" => Intrinsic {
2488 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2489 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2490 definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2492 "ld4q_dup_s64" => Intrinsic {
2493 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2494 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2495 definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2497 "ld4q_dup_u64" => Intrinsic {
2498 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2499 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2500 definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2502 "ld4q_dup_f32" => Intrinsic {
2503 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2504 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2505 definition: Named("llvm.aarch64.neon.ld4.v4f32.p0f32")
2507 "ld4q_dup_f64" => Intrinsic {
2508 inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2509 output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2510 definition: Named("llvm.aarch64.neon.ld4.v2f64.p0f64")
2512 "padd_s8" => Intrinsic {
2513 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2515 definition: Named("llvm.aarch64.neon.addp.v8i8")
2517 "padd_u8" => Intrinsic {
2518 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2520 definition: Named("llvm.aarch64.neon.addp.v8i8")
2522 "padd_s16" => Intrinsic {
2523 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2525 definition: Named("llvm.aarch64.neon.addp.v4i16")
2527 "padd_u16" => Intrinsic {
2528 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2530 definition: Named("llvm.aarch64.neon.addp.v4i16")
2532 "padd_s32" => Intrinsic {
2533 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2535 definition: Named("llvm.aarch64.neon.addp.v2i32")
2537 "padd_u32" => Intrinsic {
2538 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2540 definition: Named("llvm.aarch64.neon.addp.v2i32")
2542 "padd_f32" => Intrinsic {
2543 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2545 definition: Named("llvm.aarch64.neon.addp.v2f32")
2547 "paddq_s8" => Intrinsic {
2548 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2550 definition: Named("llvm.aarch64.neon.addp.v16i8")
2552 "paddq_u8" => Intrinsic {
2553 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2555 definition: Named("llvm.aarch64.neon.addp.v16i8")
2557 "paddq_s16" => Intrinsic {
2558 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2560 definition: Named("llvm.aarch64.neon.addp.v8i16")
2562 "paddq_u16" => Intrinsic {
2563 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2565 definition: Named("llvm.aarch64.neon.addp.v8i16")
2567 "paddq_s32" => Intrinsic {
2568 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2570 definition: Named("llvm.aarch64.neon.addp.v4i32")
2572 "paddq_u32" => Intrinsic {
2573 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2575 definition: Named("llvm.aarch64.neon.addp.v4i32")
2577 "paddq_f32" => Intrinsic {
2578 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2580 definition: Named("llvm.aarch64.neon.addp.v4f32")
2582 "paddq_s64" => Intrinsic {
2583 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2585 definition: Named("llvm.aarch64.neon.addp.v2i64")
2587 "paddq_u64" => Intrinsic {
2588 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2590 definition: Named("llvm.aarch64.neon.addp.v2i64")
2592 "paddq_f64" => Intrinsic {
2593 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2595 definition: Named("llvm.aarch64.neon.addp.v2f64")
2597 "paddl_s16" => Intrinsic {
2598 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
2600 definition: Named("llvm.aarch64.neon.saddlp.v4i16.v8i8")
2602 "paddl_u16" => Intrinsic {
2603 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
2605 definition: Named("llvm.aarch64.neon.uaddlp.v4i16.v8i8")
2607 "paddl_s32" => Intrinsic {
2608 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
2610 definition: Named("llvm.aarch64.neon.saddlp.v2i32.v4i16")
2612 "paddl_u32" => Intrinsic {
2613 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
2615 definition: Named("llvm.aarch64.neon.uaddlp.v2i32.v4i16")
2617 "paddl_s64" => Intrinsic {
2618 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
2620 definition: Named("llvm.aarch64.neon.saddlp.v1i64.v2i32")
2622 "paddl_u64" => Intrinsic {
2623 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
2625 definition: Named("llvm.aarch64.neon.uaddlp.v1i64.v2i32")
2627 "paddlq_s16" => Intrinsic {
2628 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
2630 definition: Named("llvm.aarch64.neon.saddlp.v8i16.v16i8")
2632 "paddlq_u16" => Intrinsic {
2633 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
2635 definition: Named("llvm.aarch64.neon.uaddlp.v8i16.v16i8")
2637 "paddlq_s32" => Intrinsic {
2638 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
2640 definition: Named("llvm.aarch64.neon.saddlp.v4i32.v8i16")
2642 "paddlq_u32" => Intrinsic {
2643 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
2645 definition: Named("llvm.aarch64.neon.uaddlp.v4i32.v8i16")
2647 "paddlq_s64" => Intrinsic {
2648 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
2650 definition: Named("llvm.aarch64.neon.saddlp.v2i64.v4i32")
2652 "paddlq_u64" => Intrinsic {
2653 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
2655 definition: Named("llvm.aarch64.neon.uaddlp.v2i64.v4i32")
2657 "pmax_s8" => Intrinsic {
2658 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2660 definition: Named("llvm.aarch64.neon.smaxp.v8i8")
2662 "pmax_u8" => Intrinsic {
2663 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2665 definition: Named("llvm.aarch64.neon.umaxp.v8i8")
2667 "pmax_s16" => Intrinsic {
2668 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2670 definition: Named("llvm.aarch64.neon.smaxp.v4i16")
2672 "pmax_u16" => Intrinsic {
2673 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2675 definition: Named("llvm.aarch64.neon.umaxp.v4i16")
2677 "pmax_s32" => Intrinsic {
2678 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2680 definition: Named("llvm.aarch64.neon.smaxp.v2i32")
2682 "pmax_u32" => Intrinsic {
2683 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2685 definition: Named("llvm.aarch64.neon.umaxp.v2i32")
2687 "pmax_f32" => Intrinsic {
2688 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2690 definition: Named("llvm.aarch64.neon.fmaxp.v2f32")
2692 "pmaxq_s8" => Intrinsic {
2693 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2695 definition: Named("llvm.aarch64.neon.smaxp.v16i8")
2697 "pmaxq_u8" => Intrinsic {
2698 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2700 definition: Named("llvm.aarch64.neon.umaxp.v16i8")
2702 "pmaxq_s16" => Intrinsic {
2703 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2705 definition: Named("llvm.aarch64.neon.smaxp.v8i16")
2707 "pmaxq_u16" => Intrinsic {
2708 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2710 definition: Named("llvm.aarch64.neon.umaxp.v8i16")
2712 "pmaxq_s32" => Intrinsic {
2713 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2715 definition: Named("llvm.aarch64.neon.smaxp.v4i32")
2717 "pmaxq_u32" => Intrinsic {
2718 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2720 definition: Named("llvm.aarch64.neon.umaxp.v4i32")
2722 "pmaxq_f32" => Intrinsic {
2723 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2725 definition: Named("llvm.aarch64.neon.fmaxp.v4f32")
2727 "pmaxq_s64" => Intrinsic {
2728 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2730 definition: Named("llvm.aarch64.neon.smaxp.v2i64")
2732 "pmaxq_u64" => Intrinsic {
2733 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2735 definition: Named("llvm.aarch64.neon.umaxp.v2i64")
2737 "pmaxq_f64" => Intrinsic {
2738 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2740 definition: Named("llvm.aarch64.neon.fmaxp.v2f64")
2742 "pmin_s8" => Intrinsic {
2743 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2745 definition: Named("llvm.aarch64.neon.sminp.v8i8")
2747 "pmin_u8" => Intrinsic {
2748 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2750 definition: Named("llvm.aarch64.neon.uminp.v8i8")
2752 "pmin_s16" => Intrinsic {
2753 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2755 definition: Named("llvm.aarch64.neon.sminp.v4i16")
2757 "pmin_u16" => Intrinsic {
2758 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2760 definition: Named("llvm.aarch64.neon.uminp.v4i16")
2762 "pmin_s32" => Intrinsic {
2763 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2765 definition: Named("llvm.aarch64.neon.sminp.v2i32")
2767 "pmin_u32" => Intrinsic {
2768 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2770 definition: Named("llvm.aarch64.neon.uminp.v2i32")
2772 "pmin_f32" => Intrinsic {
2773 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2775 definition: Named("llvm.aarch64.neon.fminp.v2f32")
2777 "pminq_s8" => Intrinsic {
2778 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2780 definition: Named("llvm.aarch64.neon.sminp.v16i8")
2782 "pminq_u8" => Intrinsic {
2783 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2785 definition: Named("llvm.aarch64.neon.uminp.v16i8")
2787 "pminq_s16" => Intrinsic {
2788 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2790 definition: Named("llvm.aarch64.neon.sminp.v8i16")
2792 "pminq_u16" => Intrinsic {
2793 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2795 definition: Named("llvm.aarch64.neon.uminp.v8i16")
2797 "pminq_s32" => Intrinsic {
2798 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2800 definition: Named("llvm.aarch64.neon.sminp.v4i32")
2802 "pminq_u32" => Intrinsic {
2803 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2805 definition: Named("llvm.aarch64.neon.uminp.v4i32")
2807 "pminq_f32" => Intrinsic {
2808 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2810 definition: Named("llvm.aarch64.neon.fminp.v4f32")
2812 "pminq_s64" => Intrinsic {
2813 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2815 definition: Named("llvm.aarch64.neon.sminp.v2i64")
2817 "pminq_u64" => Intrinsic {
2818 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2820 definition: Named("llvm.aarch64.neon.uminp.v2i64")
2822 "pminq_f64" => Intrinsic {
2823 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2825 definition: Named("llvm.aarch64.neon.fminp.v2f64")
2827 "pmaxnm_s8" => Intrinsic {
2828 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2830 definition: Named("llvm.aarch64.neon.smaxnmp.v8i8")
2832 "pmaxnm_u8" => Intrinsic {
2833 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2835 definition: Named("llvm.aarch64.neon.umaxnmp.v8i8")
2837 "pmaxnm_s16" => Intrinsic {
2838 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2840 definition: Named("llvm.aarch64.neon.smaxnmp.v4i16")
2842 "pmaxnm_u16" => Intrinsic {
2843 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2845 definition: Named("llvm.aarch64.neon.umaxnmp.v4i16")
2847 "pmaxnm_s32" => Intrinsic {
2848 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2850 definition: Named("llvm.aarch64.neon.smaxnmp.v2i32")
2852 "pmaxnm_u32" => Intrinsic {
2853 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2855 definition: Named("llvm.aarch64.neon.umaxnmp.v2i32")
2857 "pmaxnm_f32" => Intrinsic {
2858 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2860 definition: Named("llvm.aarch64.neon.fmaxnmp.v2f32")
2862 "pmaxnmq_s8" => Intrinsic {
2863 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2865 definition: Named("llvm.aarch64.neon.smaxnmp.v16i8")
2867 "pmaxnmq_u8" => Intrinsic {
2868 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2870 definition: Named("llvm.aarch64.neon.umaxnmp.v16i8")
2872 "pmaxnmq_s16" => Intrinsic {
2873 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2875 definition: Named("llvm.aarch64.neon.smaxnmp.v8i16")
2877 "pmaxnmq_u16" => Intrinsic {
2878 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2880 definition: Named("llvm.aarch64.neon.umaxnmp.v8i16")
2882 "pmaxnmq_s32" => Intrinsic {
2883 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2885 definition: Named("llvm.aarch64.neon.smaxnmp.v4i32")
2887 "pmaxnmq_u32" => Intrinsic {
2888 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2890 definition: Named("llvm.aarch64.neon.umaxnmp.v4i32")
2892 "pmaxnmq_f32" => Intrinsic {
2893 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2895 definition: Named("llvm.aarch64.neon.fmaxnmp.v4f32")
2897 "pmaxnmq_s64" => Intrinsic {
2898 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2900 definition: Named("llvm.aarch64.neon.smaxnmp.v2i64")
2902 "pmaxnmq_u64" => Intrinsic {
2903 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2905 definition: Named("llvm.aarch64.neon.umaxnmp.v2i64")
2907 "pmaxnmq_f64" => Intrinsic {
2908 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2910 definition: Named("llvm.aarch64.neon.fmaxnmp.v2f64")
2912 "pminnm_f32" => Intrinsic {
2913 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2915 definition: Named("llvm.aarch64.neon.fminnmp.v2f32")
2917 "pminnmq_f32" => Intrinsic {
2918 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2920 definition: Named("llvm.aarch64.neon.fminnmp.v4f32")
2922 "pminnmq_f64" => Intrinsic {
2923 inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2925 definition: Named("llvm.aarch64.neon.fminnmp.v2f64")
2927 "addv_s8" => Intrinsic {
2928 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
2930 definition: Named("llvm.aarch64.neon.saddv.i8.v8i8")
2932 "addv_u8" => Intrinsic {
2933 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
2935 definition: Named("llvm.aarch64.neon.uaddv.i8.v8i8")
2937 "addv_s16" => Intrinsic {
2938 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
2940 definition: Named("llvm.aarch64.neon.saddv.i16.v4i16")
2942 "addv_u16" => Intrinsic {
2943 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
2945 definition: Named("llvm.aarch64.neon.uaddv.i16.v4i16")
2947 "addv_s32" => Intrinsic {
2948 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
2950 definition: Named("llvm.aarch64.neon.saddv.i32.v2i32")
2952 "addv_u32" => Intrinsic {
2953 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
2955 definition: Named("llvm.aarch64.neon.uaddv.i32.v2i32")
2957 "addv_f32" => Intrinsic {
2958 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
2960 definition: Named("llvm.aarch64.neon.faddv.f32.v2f32")
2962 "addvq_s8" => Intrinsic {
2963 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
2965 definition: Named("llvm.aarch64.neon.saddv.i8.v16i8")
2967 "addvq_u8" => Intrinsic {
2968 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
2970 definition: Named("llvm.aarch64.neon.uaddv.i8.v16i8")
2972 "addvq_s16" => Intrinsic {
2973 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
2975 definition: Named("llvm.aarch64.neon.saddv.i16.v8i16")
2977 "addvq_u16" => Intrinsic {
2978 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
2980 definition: Named("llvm.aarch64.neon.uaddv.i16.v8i16")
2982 "addvq_s32" => Intrinsic {
2983 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
2985 definition: Named("llvm.aarch64.neon.saddv.i32.v4i32")
2987 "addvq_u32" => Intrinsic {
2988 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
2990 definition: Named("llvm.aarch64.neon.uaddv.i32.v4i32")
2992 "addvq_f32" => Intrinsic {
2993 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
2995 definition: Named("llvm.aarch64.neon.faddv.f32.v4f32")
2997 "addvq_s64" => Intrinsic {
2998 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
3000 definition: Named("llvm.aarch64.neon.saddv.i64.v2i64")
3002 "addvq_u64" => Intrinsic {
3003 inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
3005 definition: Named("llvm.aarch64.neon.uaddv.i64.v2i64")
3007 "addvq_f64" => Intrinsic {
3008 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3010 definition: Named("llvm.aarch64.neon.faddv.f64.v2f64")
3012 "addlv_s8" => Intrinsic {
3013 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3015 definition: Named("llvm.aarch64.neon.saddlv.i16.v8i8")
3017 "addlv_u8" => Intrinsic {
3018 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3020 definition: Named("llvm.aarch64.neon.uaddlv.i16.v8i8")
3022 "addlv_s16" => Intrinsic {
3023 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3025 definition: Named("llvm.aarch64.neon.saddlv.i32.v4i16")
3027 "addlv_u16" => Intrinsic {
3028 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3030 definition: Named("llvm.aarch64.neon.uaddlv.i32.v4i16")
3032 "addlv_s32" => Intrinsic {
3033 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3035 definition: Named("llvm.aarch64.neon.saddlv.i64.v2i32")
3037 "addlv_u32" => Intrinsic {
3038 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3040 definition: Named("llvm.aarch64.neon.uaddlv.i64.v2i32")
3042 "addlvq_s8" => Intrinsic {
3043 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3045 definition: Named("llvm.aarch64.neon.saddlv.i16.v16i8")
3047 "addlvq_u8" => Intrinsic {
3048 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3050 definition: Named("llvm.aarch64.neon.uaddlv.i16.v16i8")
3052 "addlvq_s16" => Intrinsic {
3053 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3055 definition: Named("llvm.aarch64.neon.saddlv.i32.v8i16")
3057 "addlvq_u16" => Intrinsic {
3058 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3060 definition: Named("llvm.aarch64.neon.uaddlv.i32.v8i16")
3062 "addlvq_s32" => Intrinsic {
3063 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3065 definition: Named("llvm.aarch64.neon.saddlv.i64.v4i32")
3067 "addlvq_u32" => Intrinsic {
3068 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3070 definition: Named("llvm.aarch64.neon.uaddlv.i64.v4i32")
3072 "maxv_s8" => Intrinsic {
3073 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3075 definition: Named("llvm.aarch64.neon.smaxv.i8.v8i8")
3077 "maxv_u8" => Intrinsic {
3078 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3080 definition: Named("llvm.aarch64.neon.umaxv.i8.v8i8")
3082 "maxv_s16" => Intrinsic {
3083 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3085 definition: Named("llvm.aarch64.neon.smaxv.i16.v4i16")
3087 "maxv_u16" => Intrinsic {
3088 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3090 definition: Named("llvm.aarch64.neon.umaxv.i16.v4i16")
3092 "maxv_s32" => Intrinsic {
3093 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3095 definition: Named("llvm.aarch64.neon.smaxv.i32.v2i32")
3097 "maxv_u32" => Intrinsic {
3098 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3100 definition: Named("llvm.aarch64.neon.umaxv.i32.v2i32")
3102 "maxv_f32" => Intrinsic {
3103 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3105 definition: Named("llvm.aarch64.neon.fmaxv.f32.v2f32")
3107 "maxvq_s8" => Intrinsic {
3108 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3110 definition: Named("llvm.aarch64.neon.smaxv.i8.v16i8")
3112 "maxvq_u8" => Intrinsic {
3113 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3115 definition: Named("llvm.aarch64.neon.umaxv.i8.v16i8")
3117 "maxvq_s16" => Intrinsic {
3118 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3120 definition: Named("llvm.aarch64.neon.smaxv.i16.v8i16")
3122 "maxvq_u16" => Intrinsic {
3123 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3125 definition: Named("llvm.aarch64.neon.umaxv.i16.v8i16")
3127 "maxvq_s32" => Intrinsic {
3128 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3130 definition: Named("llvm.aarch64.neon.smaxv.i32.v4i32")
3132 "maxvq_u32" => Intrinsic {
3133 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3135 definition: Named("llvm.aarch64.neon.umaxv.i32.v4i32")
3137 "maxvq_f32" => Intrinsic {
3138 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3140 definition: Named("llvm.aarch64.neon.fmaxv.f32.v4f32")
3142 "maxvq_f64" => Intrinsic {
3143 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3145 definition: Named("llvm.aarch64.neon.fmaxv.f64.v2f64")
3147 "minv_s8" => Intrinsic {
3148 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3150 definition: Named("llvm.aarch64.neon.sminv.i8.v8i8")
3152 "minv_u8" => Intrinsic {
3153 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3155 definition: Named("llvm.aarch64.neon.uminv.i8.v8i8")
3157 "minv_s16" => Intrinsic {
3158 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3160 definition: Named("llvm.aarch64.neon.sminv.i16.v4i16")
3162 "minv_u16" => Intrinsic {
3163 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3165 definition: Named("llvm.aarch64.neon.uminv.i16.v4i16")
3167 "minv_s32" => Intrinsic {
3168 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3170 definition: Named("llvm.aarch64.neon.sminv.i32.v2i32")
3172 "minv_u32" => Intrinsic {
3173 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3175 definition: Named("llvm.aarch64.neon.uminv.i32.v2i32")
3177 "minv_f32" => Intrinsic {
3178 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3180 definition: Named("llvm.aarch64.neon.fminv.f32.v2f32")
3182 "minvq_s8" => Intrinsic {
3183 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3185 definition: Named("llvm.aarch64.neon.sminv.i8.v16i8")
3187 "minvq_u8" => Intrinsic {
3188 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3190 definition: Named("llvm.aarch64.neon.uminv.i8.v16i8")
3192 "minvq_s16" => Intrinsic {
3193 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3195 definition: Named("llvm.aarch64.neon.sminv.i16.v8i16")
3197 "minvq_u16" => Intrinsic {
3198 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3200 definition: Named("llvm.aarch64.neon.uminv.i16.v8i16")
3202 "minvq_s32" => Intrinsic {
3203 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3205 definition: Named("llvm.aarch64.neon.sminv.i32.v4i32")
3207 "minvq_u32" => Intrinsic {
3208 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3210 definition: Named("llvm.aarch64.neon.uminv.i32.v4i32")
3212 "minvq_f32" => Intrinsic {
3213 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3215 definition: Named("llvm.aarch64.neon.fminv.f32.v4f32")
3217 "minvq_f64" => Intrinsic {
3218 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3220 definition: Named("llvm.aarch64.neon.fminv.f64.v2f64")
3222 "maxnmv_f32" => Intrinsic {
3223 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3225 definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v2f32")
3227 "maxnmvq_f32" => Intrinsic {
3228 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3230 definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v4f32")
3232 "maxnmvq_f64" => Intrinsic {
3233 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3235 definition: Named("llvm.aarch64.neon.fmaxnmv.f64.v2f64")
3237 "minnmv_f32" => Intrinsic {
3238 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3240 definition: Named("llvm.aarch64.neon.fminnmv.f32.v2f32")
3242 "minnmvq_f32" => Intrinsic {
3243 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3245 definition: Named("llvm.aarch64.neon.fminnmv.f32.v4f32")
3247 "minnmvq_f64" => Intrinsic {
3248 inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3250 definition: Named("llvm.aarch64.neon.fminnmv.f64.v2f64")
3252 "qtbl1_s8" => Intrinsic {
3253 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x8]; &INPUTS },
3255 definition: Named("llvm.aarch64.neon.tbl1.v8i8")
3257 "qtbl1_u8" => Intrinsic {
3258 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x8]; &INPUTS },
3260 definition: Named("llvm.aarch64.neon.tbl1.v8i8")
3262 "qtbl1q_s8" => Intrinsic {
3263 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS },
3265 definition: Named("llvm.aarch64.neon.tbl1.v16i8")
3267 "qtbl1q_u8" => Intrinsic {
3268 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
3270 definition: Named("llvm.aarch64.neon.tbl1.v16i8")
3272 "qtbx1_s8" => Intrinsic {
3273 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x16, &::U8x8]; &INPUTS },
3275 definition: Named("llvm.aarch64.neon.tbx1.v8i8")
3277 "qtbx1_u8" => Intrinsic {
3278 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x16, &::U8x8]; &INPUTS },
3280 definition: Named("llvm.aarch64.neon.tbx1.v8i8")
3282 "qtbx1q_s8" => Intrinsic {
3283 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::U8x16]; &INPUTS },
3285 definition: Named("llvm.aarch64.neon.tbx1.v16i8")
3287 "qtbx1q_u8" => Intrinsic {
3288 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &INPUTS },
3290 definition: Named("llvm.aarch64.neon.tbx1.v16i8")
3292 "qtbl2_s8" => Intrinsic {
3293 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3295 definition: Named("llvm.aarch64.neon.tbl2.v8i8")
3297 "qtbl2_u8" => Intrinsic {
3298 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3300 definition: Named("llvm.aarch64.neon.tbl2.v8i8")
3302 "qtbl2q_s8" => Intrinsic {
3303 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3305 definition: Named("llvm.aarch64.neon.tbl2.v16i8")
3307 "qtbl2q_u8" => Intrinsic {
3308 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3310 definition: Named("llvm.aarch64.neon.tbl2.v16i8")
3312 "qtbx2_s8" => Intrinsic {
3313 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3315 definition: Named("llvm.aarch64.neon.tbx2.v8i8")
3317 "qtbx2_u8" => Intrinsic {
3318 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3320 definition: Named("llvm.aarch64.neon.tbx2.v8i8")
3322 "qtbx2q_s8" => Intrinsic {
3323 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3325 definition: Named("llvm.aarch64.neon.tbx2.v16i8")
3327 "qtbx2q_u8" => Intrinsic {
3328 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3330 definition: Named("llvm.aarch64.neon.tbx2.v16i8")
3332 "qtbl3_s8" => Intrinsic {
3333 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3335 definition: Named("llvm.aarch64.neon.tbl3.v8i8")
3337 "qtbl3_u8" => Intrinsic {
3338 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3340 definition: Named("llvm.aarch64.neon.tbl3.v8i8")
3342 "qtbl3q_s8" => Intrinsic {
3343 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3345 definition: Named("llvm.aarch64.neon.tbl3.v16i8")
3347 "qtbl3q_u8" => Intrinsic {
3348 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3350 definition: Named("llvm.aarch64.neon.tbl3.v16i8")
3352 "qtbx3_s8" => Intrinsic {
3353 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3355 definition: Named("llvm.aarch64.neon.tbx3.v8i8")
3357 "qtbx3_u8" => Intrinsic {
3358 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3360 definition: Named("llvm.aarch64.neon.tbx3.v8i8")
3362 "qtbx3q_s8" => Intrinsic {
3363 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3365 definition: Named("llvm.aarch64.neon.tbx3.v16i8")
3367 "qtbx3q_u8" => Intrinsic {
3368 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3370 definition: Named("llvm.aarch64.neon.tbx3.v16i8")
3372 "qtbl4_s8" => Intrinsic {
3373 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3375 definition: Named("llvm.aarch64.neon.tbl4.v8i8")
3377 "qtbl4_u8" => Intrinsic {
3378 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3380 definition: Named("llvm.aarch64.neon.tbl4.v8i8")
3382 "qtbl4q_s8" => Intrinsic {
3383 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3385 definition: Named("llvm.aarch64.neon.tbl4.v16i8")
3387 "qtbl4q_u8" => Intrinsic {
3388 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3390 definition: Named("llvm.aarch64.neon.tbl4.v16i8")
3392 "qtbx4_s8" => Intrinsic {
3393 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3395 definition: Named("llvm.aarch64.neon.tbx4.v8i8")
3397 "qtbx4_u8" => Intrinsic {
3398 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3400 definition: Named("llvm.aarch64.neon.tbx4.v8i8")
3402 "qtbx4q_s8" => Intrinsic {
3403 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3405 definition: Named("llvm.aarch64.neon.tbx4.v16i8")
3407 "qtbx4q_u8" => Intrinsic {
3408 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3410 definition: Named("llvm.aarch64.neon.tbx4.v16i8")