src/librustc_platform_intrinsics/aarch64.rs

   1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
   2 // file at the top-level directory of this distribution and at
   3 // http://rust-lang.org/COPYRIGHT.
   4 //
   5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
   6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
   7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
   8 // option. This file may not be copied, modified, or distributed
   9 // except according to those terms.
  10
  11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
  12 // ignore-tidy-linelength
  13
  14 #![allow(unused_imports)]
  15
  16 use {Intrinsic, Type};
  17 use IntrinsicDef::Named;
  18
  19 pub fn find(name: &str) -> Option<Intrinsic> {
  20     if !name.starts_with("aarch64_v") { return None }
  21     Some(match &name["aarch64_v".len()..] {
  22         "hadd_s8" => Intrinsic {
  23             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  24             output: &::I8x8,
  25             definition: Named("llvm.aarch64.neon.shadd.v8i8")
  26         },
  27         "hadd_u8" => Intrinsic {
  28             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  29             output: &::U8x8,
  30             definition: Named("llvm.aarch64.neon.uhadd.v8i8")
  31         },
  32         "hadd_s16" => Intrinsic {
  33             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  34             output: &::I16x4,
  35             definition: Named("llvm.aarch64.neon.shadd.v4i16")
  36         },
  37         "hadd_u16" => Intrinsic {
  38             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
  39             output: &::U16x4,
  40             definition: Named("llvm.aarch64.neon.uhadd.v4i16")
  41         },
  42         "hadd_s32" => Intrinsic {
  43             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
  44             output: &::I32x2,
  45             definition: Named("llvm.aarch64.neon.shadd.v2i32")
  46         },
  47         "hadd_u32" => Intrinsic {
  48             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
  49             output: &::U32x2,
  50             definition: Named("llvm.aarch64.neon.uhadd.v2i32")
  51         },
  52         "haddq_s8" => Intrinsic {
  53             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
  54             output: &::I8x16,
  55             definition: Named("llvm.aarch64.neon.shadd.v16i8")
  56         },
  57         "haddq_u8" => Intrinsic {
  58             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
  59             output: &::U8x16,
  60             definition: Named("llvm.aarch64.neon.uhadd.v16i8")
  61         },
  62         "haddq_s16" => Intrinsic {
  63             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
  64             output: &::I16x8,
  65             definition: Named("llvm.aarch64.neon.shadd.v8i16")
  66         },
  67         "haddq_u16" => Intrinsic {
  68             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
  69             output: &::U16x8,
  70             definition: Named("llvm.aarch64.neon.uhadd.v8i16")
  71         },
  72         "haddq_s32" => Intrinsic {
  73             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
  74             output: &::I32x4,
  75             definition: Named("llvm.aarch64.neon.shadd.v4i32")
  76         },
  77         "haddq_u32" => Intrinsic {
  78             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
  79             output: &::U32x4,
  80             definition: Named("llvm.aarch64.neon.uhadd.v4i32")
  81         },
  82         "rhadd_s8" => Intrinsic {
  83             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
  84             output: &::I8x8,
  85             definition: Named("llvm.aarch64.neon.srhadd.v8i8")
  86         },
  87         "rhadd_u8" => Intrinsic {
  88             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
  89             output: &::U8x8,
  90             definition: Named("llvm.aarch64.neon.urhadd.v8i8")
  91         },
  92         "rhadd_s16" => Intrinsic {
  93             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
  94             output: &::I16x4,
  95             definition: Named("llvm.aarch64.neon.srhadd.v4i16")
  96         },
  97         "rhadd_u16" => Intrinsic {
  98             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
  99             output: &::U16x4,
 100             definition: Named("llvm.aarch64.neon.urhadd.v4i16")
 101         },
 102         "rhadd_s32" => Intrinsic {
 103             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 104             output: &::I32x2,
 105             definition: Named("llvm.aarch64.neon.srhadd.v2i32")
 106         },
 107         "rhadd_u32" => Intrinsic {
 108             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 109             output: &::U32x2,
 110             definition: Named("llvm.aarch64.neon.urhadd.v2i32")
 111         },
 112         "rhaddq_s8" => Intrinsic {
 113             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 114             output: &::I8x16,
 115             definition: Named("llvm.aarch64.neon.srhadd.v16i8")
 116         },
 117         "rhaddq_u8" => Intrinsic {
 118             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 119             output: &::U8x16,
 120             definition: Named("llvm.aarch64.neon.urhadd.v16i8")
 121         },
 122         "rhaddq_s16" => Intrinsic {
 123             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 124             output: &::I16x8,
 125             definition: Named("llvm.aarch64.neon.srhadd.v8i16")
 126         },
 127         "rhaddq_u16" => Intrinsic {
 128             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 129             output: &::U16x8,
 130             definition: Named("llvm.aarch64.neon.urhadd.v8i16")
 131         },
 132         "rhaddq_s32" => Intrinsic {
 133             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 134             output: &::I32x4,
 135             definition: Named("llvm.aarch64.neon.srhadd.v4i32")
 136         },
 137         "rhaddq_u32" => Intrinsic {
 138             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 139             output: &::U32x4,
 140             definition: Named("llvm.aarch64.neon.urhadd.v4i32")
 141         },
 142         "qadd_s8" => Intrinsic {
 143             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 144             output: &::I8x8,
 145             definition: Named("llvm.aarch64.neon.sqadd.v8i8")
 146         },
 147         "qadd_u8" => Intrinsic {
 148             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 149             output: &::U8x8,
 150             definition: Named("llvm.aarch64.neon.uqadd.v8i8")
 151         },
 152         "qadd_s16" => Intrinsic {
 153             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 154             output: &::I16x4,
 155             definition: Named("llvm.aarch64.neon.sqadd.v4i16")
 156         },
 157         "qadd_u16" => Intrinsic {
 158             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 159             output: &::U16x4,
 160             definition: Named("llvm.aarch64.neon.uqadd.v4i16")
 161         },
 162         "qadd_s32" => Intrinsic {
 163             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 164             output: &::I32x2,
 165             definition: Named("llvm.aarch64.neon.sqadd.v2i32")
 166         },
 167         "qadd_u32" => Intrinsic {
 168             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 169             output: &::U32x2,
 170             definition: Named("llvm.aarch64.neon.uqadd.v2i32")
 171         },
 172         "qadd_s64" => Intrinsic {
 173             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 174             output: &::I64x1,
 175             definition: Named("llvm.aarch64.neon.sqadd.v1i64")
 176         },
 177         "qadd_u64" => Intrinsic {
 178             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 179             output: &::U64x1,
 180             definition: Named("llvm.aarch64.neon.uqadd.v1i64")
 181         },
 182         "qaddq_s8" => Intrinsic {
 183             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 184             output: &::I8x16,
 185             definition: Named("llvm.aarch64.neon.sqadd.v16i8")
 186         },
 187         "qaddq_u8" => Intrinsic {
 188             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 189             output: &::U8x16,
 190             definition: Named("llvm.aarch64.neon.uqadd.v16i8")
 191         },
 192         "qaddq_s16" => Intrinsic {
 193             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 194             output: &::I16x8,
 195             definition: Named("llvm.aarch64.neon.sqadd.v8i16")
 196         },
 197         "qaddq_u16" => Intrinsic {
 198             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 199             output: &::U16x8,
 200             definition: Named("llvm.aarch64.neon.uqadd.v8i16")
 201         },
 202         "qaddq_s32" => Intrinsic {
 203             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 204             output: &::I32x4,
 205             definition: Named("llvm.aarch64.neon.sqadd.v4i32")
 206         },
 207         "qaddq_u32" => Intrinsic {
 208             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 209             output: &::U32x4,
 210             definition: Named("llvm.aarch64.neon.uqadd.v4i32")
 211         },
 212         "qaddq_s64" => Intrinsic {
 213             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 214             output: &::I64x2,
 215             definition: Named("llvm.aarch64.neon.sqadd.v2i64")
 216         },
 217         "qaddq_u64" => Intrinsic {
 218             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 219             output: &::U64x2,
 220             definition: Named("llvm.aarch64.neon.uqadd.v2i64")
 221         },
 222         "uqadd_s8" => Intrinsic {
 223             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS },
 224             output: &::I8x16,
 225             definition: Named("llvm.aarch64.neon.suqadd.v16i8")
 226         },
 227         "uqadd_s16" => Intrinsic {
 228             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U16x8]; &INPUTS },
 229             output: &::I16x8,
 230             definition: Named("llvm.aarch64.neon.suqadd.v8i16")
 231         },
 232         "uqadd_s32" => Intrinsic {
 233             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32x4]; &INPUTS },
 234             output: &::I32x4,
 235             definition: Named("llvm.aarch64.neon.suqadd.v4i32")
 236         },
 237         "uqadd_s64" => Intrinsic {
 238             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U64x2]; &INPUTS },
 239             output: &::I64x2,
 240             definition: Named("llvm.aarch64.neon.suqadd.v2i64")
 241         },
 242         "sqadd_u8" => Intrinsic {
 243             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 244             output: &::U8x16,
 245             definition: Named("llvm.aarch64.neon.usqadd.v16i8")
 246         },
 247         "sqadd_u16" => Intrinsic {
 248             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 249             output: &::U16x8,
 250             definition: Named("llvm.aarch64.neon.usqadd.v8i16")
 251         },
 252         "sqadd_u32" => Intrinsic {
 253             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 254             output: &::U32x4,
 255             definition: Named("llvm.aarch64.neon.usqadd.v4i32")
 256         },
 257         "sqadd_u64" => Intrinsic {
 258             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 259             output: &::U64x2,
 260             definition: Named("llvm.aarch64.neon.usqadd.v2i64")
 261         },
 262         "raddhn_s16" => Intrinsic {
 263             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 264             output: &::I8x8,
 265             definition: Named("llvm.aarch64.neon.raddhn.v8i8")
 266         },
 267         "raddhn_u16" => Intrinsic {
 268             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 269             output: &::U8x8,
 270             definition: Named("llvm.aarch64.neon.raddhn.v8i8")
 271         },
 272         "raddhn_s32" => Intrinsic {
 273             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 274             output: &::I16x4,
 275             definition: Named("llvm.aarch64.neon.raddhn.v4i16")
 276         },
 277         "raddhn_u32" => Intrinsic {
 278             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 279             output: &::U16x4,
 280             definition: Named("llvm.aarch64.neon.raddhn.v4i16")
 281         },
 282         "raddhn_s64" => Intrinsic {
 283             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 284             output: &::I32x2,
 285             definition: Named("llvm.aarch64.neon.raddhn.v2i32")
 286         },
 287         "raddhn_u64" => Intrinsic {
 288             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 289             output: &::U32x2,
 290             definition: Named("llvm.aarch64.neon.raddhn.v2i32")
 291         },
 292         "fmulx_f32" => Intrinsic {
 293             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 294             output: &::F32x2,
 295             definition: Named("llvm.aarch64.neon.fmulx.v2f32")
 296         },
 297         "fmulx_f64" => Intrinsic {
 298             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 299             output: &::F64x1,
 300             definition: Named("llvm.aarch64.neon.fmulx.v1f64")
 301         },
 302         "fmulxq_f32" => Intrinsic {
 303             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 304             output: &::F32x4,
 305             definition: Named("llvm.aarch64.neon.fmulx.v4f32")
 306         },
 307         "fmulxq_f64" => Intrinsic {
 308             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 309             output: &::F64x2,
 310             definition: Named("llvm.aarch64.neon.fmulx.v2f64")
 311         },
 312         "fma_f32" => Intrinsic {
 313             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 314             output: &::F32x2,
 315             definition: Named("llvm.fma.v2f32")
 316         },
 317         "fma_f64" => Intrinsic {
 318             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 319             output: &::F64x1,
 320             definition: Named("llvm.fma.v1f64")
 321         },
 322         "fmaq_f32" => Intrinsic {
 323             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 324             output: &::F32x4,
 325             definition: Named("llvm.fma.v4f32")
 326         },
 327         "fmaq_f64" => Intrinsic {
 328             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 329             output: &::F64x2,
 330             definition: Named("llvm.fma.v2f64")
 331         },
 332         "qdmulh_s16" => Intrinsic {
 333             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 334             output: &::I16x4,
 335             definition: Named("llvm.aarch64.neon.sqdmulh.v4i16")
 336         },
 337         "qdmulh_s32" => Intrinsic {
 338             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 339             output: &::I32x2,
 340             definition: Named("llvm.aarch64.neon.sqdmulh.v2i32")
 341         },
 342         "qdmulhq_s16" => Intrinsic {
 343             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 344             output: &::I16x8,
 345             definition: Named("llvm.aarch64.neon.sqdmulh.v8i16")
 346         },
 347         "qdmulhq_s32" => Intrinsic {
 348             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 349             output: &::I32x4,
 350             definition: Named("llvm.aarch64.neon.sqdmulh.v4i32")
 351         },
 352         "qrdmulh_s16" => Intrinsic {
 353             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 354             output: &::I16x4,
 355             definition: Named("llvm.aarch64.neon.sqrdmulh.v4i16")
 356         },
 357         "qrdmulh_s32" => Intrinsic {
 358             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 359             output: &::I32x2,
 360             definition: Named("llvm.aarch64.neon.sqrdmulh.v2i32")
 361         },
 362         "qrdmulhq_s16" => Intrinsic {
 363             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 364             output: &::I16x8,
 365             definition: Named("llvm.aarch64.neon.sqrdmulh.v8i16")
 366         },
 367         "qrdmulhq_s32" => Intrinsic {
 368             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 369             output: &::I32x4,
 370             definition: Named("llvm.aarch64.neon.sqrdmulh.v4i32")
 371         },
 372         "mull_s8" => Intrinsic {
 373             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 374             output: &::I16x8,
 375             definition: Named("llvm.aarch64.neon.smull.v8i16")
 376         },
 377         "mull_u8" => Intrinsic {
 378             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 379             output: &::U16x8,
 380             definition: Named("llvm.aarch64.neon.umull.v8i16")
 381         },
 382         "mull_s16" => Intrinsic {
 383             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 384             output: &::I32x4,
 385             definition: Named("llvm.aarch64.neon.smull.v4i32")
 386         },
 387         "mull_u16" => Intrinsic {
 388             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 389             output: &::U32x4,
 390             definition: Named("llvm.aarch64.neon.umull.v4i32")
 391         },
 392         "mull_s32" => Intrinsic {
 393             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 394             output: &::I64x2,
 395             definition: Named("llvm.aarch64.neon.smull.v2i64")
 396         },
 397         "mull_u32" => Intrinsic {
 398             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 399             output: &::U64x2,
 400             definition: Named("llvm.aarch64.neon.umull.v2i64")
 401         },
 402         "qdmullq_s8" => Intrinsic {
 403             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 404             output: &::I16x8,
 405             definition: Named("llvm.aarch64.neon.sqdmull.v8i16")
 406         },
 407         "qdmullq_s16" => Intrinsic {
 408             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 409             output: &::I32x4,
 410             definition: Named("llvm.aarch64.neon.sqdmull.v4i32")
 411         },
 412         "hsub_s8" => Intrinsic {
 413             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 414             output: &::I8x8,
 415             definition: Named("llvm.aarch64.neon.shsub.v8i8")
 416         },
 417         "hsub_u8" => Intrinsic {
 418             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 419             output: &::U8x8,
 420             definition: Named("llvm.aarch64.neon.uhsub.v8i8")
 421         },
 422         "hsub_s16" => Intrinsic {
 423             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 424             output: &::I16x4,
 425             definition: Named("llvm.aarch64.neon.shsub.v4i16")
 426         },
 427         "hsub_u16" => Intrinsic {
 428             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 429             output: &::U16x4,
 430             definition: Named("llvm.aarch64.neon.uhsub.v4i16")
 431         },
 432         "hsub_s32" => Intrinsic {
 433             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 434             output: &::I32x2,
 435             definition: Named("llvm.aarch64.neon.shsub.v2i32")
 436         },
 437         "hsub_u32" => Intrinsic {
 438             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 439             output: &::U32x2,
 440             definition: Named("llvm.aarch64.neon.uhsub.v2i32")
 441         },
 442         "hsubq_s8" => Intrinsic {
 443             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 444             output: &::I8x16,
 445             definition: Named("llvm.aarch64.neon.shsub.v16i8")
 446         },
 447         "hsubq_u8" => Intrinsic {
 448             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 449             output: &::U8x16,
 450             definition: Named("llvm.aarch64.neon.uhsub.v16i8")
 451         },
 452         "hsubq_s16" => Intrinsic {
 453             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 454             output: &::I16x8,
 455             definition: Named("llvm.aarch64.neon.shsub.v8i16")
 456         },
 457         "hsubq_u16" => Intrinsic {
 458             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 459             output: &::U16x8,
 460             definition: Named("llvm.aarch64.neon.uhsub.v8i16")
 461         },
 462         "hsubq_s32" => Intrinsic {
 463             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 464             output: &::I32x4,
 465             definition: Named("llvm.aarch64.neon.shsub.v4i32")
 466         },
 467         "hsubq_u32" => Intrinsic {
 468             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 469             output: &::U32x4,
 470             definition: Named("llvm.aarch64.neon.uhsub.v4i32")
 471         },
 472         "qsub_s8" => Intrinsic {
 473             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 474             output: &::I8x8,
 475             definition: Named("llvm.aarch64.neon.sqsub.v8i8")
 476         },
 477         "qsub_u8" => Intrinsic {
 478             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 479             output: &::U8x8,
 480             definition: Named("llvm.aarch64.neon.uqsub.v8i8")
 481         },
 482         "qsub_s16" => Intrinsic {
 483             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 484             output: &::I16x4,
 485             definition: Named("llvm.aarch64.neon.sqsub.v4i16")
 486         },
 487         "qsub_u16" => Intrinsic {
 488             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 489             output: &::U16x4,
 490             definition: Named("llvm.aarch64.neon.uqsub.v4i16")
 491         },
 492         "qsub_s32" => Intrinsic {
 493             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 494             output: &::I32x2,
 495             definition: Named("llvm.aarch64.neon.sqsub.v2i32")
 496         },
 497         "qsub_u32" => Intrinsic {
 498             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 499             output: &::U32x2,
 500             definition: Named("llvm.aarch64.neon.uqsub.v2i32")
 501         },
 502         "qsub_s64" => Intrinsic {
 503             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 504             output: &::I64x1,
 505             definition: Named("llvm.aarch64.neon.sqsub.v1i64")
 506         },
 507         "qsub_u64" => Intrinsic {
 508             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
 509             output: &::U64x1,
 510             definition: Named("llvm.aarch64.neon.uqsub.v1i64")
 511         },
 512         "qsubq_s8" => Intrinsic {
 513             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 514             output: &::I8x16,
 515             definition: Named("llvm.aarch64.neon.sqsub.v16i8")
 516         },
 517         "qsubq_u8" => Intrinsic {
 518             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 519             output: &::U8x16,
 520             definition: Named("llvm.aarch64.neon.uqsub.v16i8")
 521         },
 522         "qsubq_s16" => Intrinsic {
 523             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 524             output: &::I16x8,
 525             definition: Named("llvm.aarch64.neon.sqsub.v8i16")
 526         },
 527         "qsubq_u16" => Intrinsic {
 528             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 529             output: &::U16x8,
 530             definition: Named("llvm.aarch64.neon.uqsub.v8i16")
 531         },
 532         "qsubq_s32" => Intrinsic {
 533             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 534             output: &::I32x4,
 535             definition: Named("llvm.aarch64.neon.sqsub.v4i32")
 536         },
 537         "qsubq_u32" => Intrinsic {
 538             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 539             output: &::U32x4,
 540             definition: Named("llvm.aarch64.neon.uqsub.v4i32")
 541         },
 542         "qsubq_s64" => Intrinsic {
 543             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 544             output: &::I64x2,
 545             definition: Named("llvm.aarch64.neon.sqsub.v2i64")
 546         },
 547         "qsubq_u64" => Intrinsic {
 548             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 549             output: &::U64x2,
 550             definition: Named("llvm.aarch64.neon.uqsub.v2i64")
 551         },
 552         "rsubhn_s16" => Intrinsic {
 553             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 554             output: &::I8x8,
 555             definition: Named("llvm.aarch64.neon.rsubhn.v8i8")
 556         },
 557         "rsubhn_u16" => Intrinsic {
 558             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 559             output: &::U8x8,
 560             definition: Named("llvm.aarch64.neon.rsubhn.v8i8")
 561         },
 562         "rsubhn_s32" => Intrinsic {
 563             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 564             output: &::I16x4,
 565             definition: Named("llvm.aarch64.neon.rsubhn.v4i16")
 566         },
 567         "rsubhn_u32" => Intrinsic {
 568             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 569             output: &::U16x4,
 570             definition: Named("llvm.aarch64.neon.rsubhn.v4i16")
 571         },
 572         "rsubhn_s64" => Intrinsic {
 573             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 574             output: &::I32x2,
 575             definition: Named("llvm.aarch64.neon.rsubhn.v2i32")
 576         },
 577         "rsubhn_u64" => Intrinsic {
 578             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
 579             output: &::U32x2,
 580             definition: Named("llvm.aarch64.neon.rsubhn.v2i32")
 581         },
 582         "abd_s8" => Intrinsic {
 583             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 584             output: &::I8x8,
 585             definition: Named("llvm.aarch64.neon.sabd.v8i8")
 586         },
 587         "abd_u8" => Intrinsic {
 588             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 589             output: &::U8x8,
 590             definition: Named("llvm.aarch64.neon.uabd.v8i8")
 591         },
 592         "abd_s16" => Intrinsic {
 593             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 594             output: &::I16x4,
 595             definition: Named("llvm.aarch64.neon.sabd.v4i16")
 596         },
 597         "abd_u16" => Intrinsic {
 598             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 599             output: &::U16x4,
 600             definition: Named("llvm.aarch64.neon.uabd.v4i16")
 601         },
 602         "abd_s32" => Intrinsic {
 603             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 604             output: &::I32x2,
 605             definition: Named("llvm.aarch64.neon.sabd.v2i32")
 606         },
 607         "abd_u32" => Intrinsic {
 608             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 609             output: &::U32x2,
 610             definition: Named("llvm.aarch64.neon.uabd.v2i32")
 611         },
 612         "abd_f32" => Intrinsic {
 613             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 614             output: &::F32x2,
 615             definition: Named("llvm.aarch64.neon.fabd.v2f32")
 616         },
 617         "abd_f64" => Intrinsic {
 618             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 619             output: &::F64x1,
 620             definition: Named("llvm.aarch64.neon.fabd.v1f64")
 621         },
 622         "abdq_s8" => Intrinsic {
 623             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 624             output: &::I8x16,
 625             definition: Named("llvm.aarch64.neon.sabd.v16i8")
 626         },
 627         "abdq_u8" => Intrinsic {
 628             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 629             output: &::U8x16,
 630             definition: Named("llvm.aarch64.neon.uabd.v16i8")
 631         },
 632         "abdq_s16" => Intrinsic {
 633             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 634             output: &::I16x8,
 635             definition: Named("llvm.aarch64.neon.sabd.v8i16")
 636         },
 637         "abdq_u16" => Intrinsic {
 638             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 639             output: &::U16x8,
 640             definition: Named("llvm.aarch64.neon.uabd.v8i16")
 641         },
 642         "abdq_s32" => Intrinsic {
 643             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 644             output: &::I32x4,
 645             definition: Named("llvm.aarch64.neon.sabd.v4i32")
 646         },
 647         "abdq_u32" => Intrinsic {
 648             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 649             output: &::U32x4,
 650             definition: Named("llvm.aarch64.neon.uabd.v4i32")
 651         },
 652         "abdq_f32" => Intrinsic {
 653             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 654             output: &::F32x4,
 655             definition: Named("llvm.aarch64.neon.fabd.v4f32")
 656         },
 657         "abdq_f64" => Intrinsic {
 658             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 659             output: &::F64x2,
 660             definition: Named("llvm.aarch64.neon.fabd.v2f64")
 661         },
 662         "max_s8" => Intrinsic {
 663             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 664             output: &::I8x8,
 665             definition: Named("llvm.aarch64.neon.smax.v8i8")
 666         },
 667         "max_u8" => Intrinsic {
 668             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 669             output: &::U8x8,
 670             definition: Named("llvm.aarch64.neon.umax.v8i8")
 671         },
 672         "max_s16" => Intrinsic {
 673             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 674             output: &::I16x4,
 675             definition: Named("llvm.aarch64.neon.smax.v4i16")
 676         },
 677         "max_u16" => Intrinsic {
 678             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 679             output: &::U16x4,
 680             definition: Named("llvm.aarch64.neon.umax.v4i16")
 681         },
 682         "max_s32" => Intrinsic {
 683             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 684             output: &::I32x2,
 685             definition: Named("llvm.aarch64.neon.smax.v2i32")
 686         },
 687         "max_u32" => Intrinsic {
 688             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 689             output: &::U32x2,
 690             definition: Named("llvm.aarch64.neon.umax.v2i32")
 691         },
 692         "max_f32" => Intrinsic {
 693             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 694             output: &::F32x2,
 695             definition: Named("llvm.aarch64.neon.fmax.v2f32")
 696         },
 697         "max_f64" => Intrinsic {
 698             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 699             output: &::F64x1,
 700             definition: Named("llvm.aarch64.neon.fmax.v1f64")
 701         },
 702         "maxq_s8" => Intrinsic {
 703             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 704             output: &::I8x16,
 705             definition: Named("llvm.aarch64.neon.smax.v16i8")
 706         },
 707         "maxq_u8" => Intrinsic {
 708             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 709             output: &::U8x16,
 710             definition: Named("llvm.aarch64.neon.umax.v16i8")
 711         },
 712         "maxq_s16" => Intrinsic {
 713             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 714             output: &::I16x8,
 715             definition: Named("llvm.aarch64.neon.smax.v8i16")
 716         },
 717         "maxq_u16" => Intrinsic {
 718             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 719             output: &::U16x8,
 720             definition: Named("llvm.aarch64.neon.umax.v8i16")
 721         },
 722         "maxq_s32" => Intrinsic {
 723             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 724             output: &::I32x4,
 725             definition: Named("llvm.aarch64.neon.smax.v4i32")
 726         },
 727         "maxq_u32" => Intrinsic {
 728             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 729             output: &::U32x4,
 730             definition: Named("llvm.aarch64.neon.umax.v4i32")
 731         },
 732         "maxq_f32" => Intrinsic {
 733             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 734             output: &::F32x4,
 735             definition: Named("llvm.aarch64.neon.fmax.v4f32")
 736         },
 737         "maxq_f64" => Intrinsic {
 738             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 739             output: &::F64x2,
 740             definition: Named("llvm.aarch64.neon.fmax.v2f64")
 741         },
 742         "min_s8" => Intrinsic {
 743             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 744             output: &::I8x8,
 745             definition: Named("llvm.aarch64.neon.smin.v8i8")
 746         },
 747         "min_u8" => Intrinsic {
 748             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
 749             output: &::U8x8,
 750             definition: Named("llvm.aarch64.neon.umin.v8i8")
 751         },
 752         "min_s16" => Intrinsic {
 753             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 754             output: &::I16x4,
 755             definition: Named("llvm.aarch64.neon.smin.v4i16")
 756         },
 757         "min_u16" => Intrinsic {
 758             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
 759             output: &::U16x4,
 760             definition: Named("llvm.aarch64.neon.umin.v4i16")
 761         },
 762         "min_s32" => Intrinsic {
 763             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 764             output: &::I32x2,
 765             definition: Named("llvm.aarch64.neon.smin.v2i32")
 766         },
 767         "min_u32" => Intrinsic {
 768             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
 769             output: &::U32x2,
 770             definition: Named("llvm.aarch64.neon.umin.v2i32")
 771         },
 772         "min_f32" => Intrinsic {
 773             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 774             output: &::F32x2,
 775             definition: Named("llvm.aarch64.neon.fmin.v2f32")
 776         },
 777         "min_f64" => Intrinsic {
 778             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 779             output: &::F64x1,
 780             definition: Named("llvm.aarch64.neon.fmin.v1f64")
 781         },
 782         "minq_s8" => Intrinsic {
 783             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 784             output: &::I8x16,
 785             definition: Named("llvm.aarch64.neon.smin.v16i8")
 786         },
 787         "minq_u8" => Intrinsic {
 788             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
 789             output: &::U8x16,
 790             definition: Named("llvm.aarch64.neon.umin.v16i8")
 791         },
 792         "minq_s16" => Intrinsic {
 793             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 794             output: &::I16x8,
 795             definition: Named("llvm.aarch64.neon.smin.v8i16")
 796         },
 797         "minq_u16" => Intrinsic {
 798             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
 799             output: &::U16x8,
 800             definition: Named("llvm.aarch64.neon.umin.v8i16")
 801         },
 802         "minq_s32" => Intrinsic {
 803             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 804             output: &::I32x4,
 805             definition: Named("llvm.aarch64.neon.smin.v4i32")
 806         },
 807         "minq_u32" => Intrinsic {
 808             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
 809             output: &::U32x4,
 810             definition: Named("llvm.aarch64.neon.umin.v4i32")
 811         },
 812         "minq_f32" => Intrinsic {
 813             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 814             output: &::F32x4,
 815             definition: Named("llvm.aarch64.neon.fmin.v4f32")
 816         },
 817         "minq_f64" => Intrinsic {
 818             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 819             output: &::F64x2,
 820             definition: Named("llvm.aarch64.neon.fmin.v2f64")
 821         },
 822         "maxnm_f32" => Intrinsic {
 823             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 824             output: &::F32x2,
 825             definition: Named("llvm.aarch64.neon.fmaxnm.v2f32")
 826         },
 827         "maxnm_f64" => Intrinsic {
 828             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 829             output: &::F64x1,
 830             definition: Named("llvm.aarch64.neon.fmaxnm.v1f64")
 831         },
 832         "maxnmq_f32" => Intrinsic {
 833             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 834             output: &::F32x4,
 835             definition: Named("llvm.aarch64.neon.fmaxnm.v4f32")
 836         },
 837         "maxnmq_f64" => Intrinsic {
 838             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 839             output: &::F64x2,
 840             definition: Named("llvm.aarch64.neon.fmaxnm.v2f64")
 841         },
 842         "minnm_f32" => Intrinsic {
 843             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
 844             output: &::F32x2,
 845             definition: Named("llvm.aarch64.neon.fminnm.v2f32")
 846         },
 847         "minnm_f64" => Intrinsic {
 848             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
 849             output: &::F64x1,
 850             definition: Named("llvm.aarch64.neon.fminnm.v1f64")
 851         },
 852         "minnmq_f32" => Intrinsic {
 853             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
 854             output: &::F32x4,
 855             definition: Named("llvm.aarch64.neon.fminnm.v4f32")
 856         },
 857         "minnmq_f64" => Intrinsic {
 858             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
 859             output: &::F64x2,
 860             definition: Named("llvm.aarch64.neon.fminnm.v2f64")
 861         },
 862         "shl_s8" => Intrinsic {
 863             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 864             output: &::I8x8,
 865             definition: Named("llvm.aarch64.neon.sshl.v8i8")
 866         },
 867         "shl_u8" => Intrinsic {
 868             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 869             output: &::U8x8,
 870             definition: Named("llvm.aarch64.neon.ushl.v8i8")
 871         },
 872         "shl_s16" => Intrinsic {
 873             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 874             output: &::I16x4,
 875             definition: Named("llvm.aarch64.neon.sshl.v4i16")
 876         },
 877         "shl_u16" => Intrinsic {
 878             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 879             output: &::U16x4,
 880             definition: Named("llvm.aarch64.neon.ushl.v4i16")
 881         },
 882         "shl_s32" => Intrinsic {
 883             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 884             output: &::I32x2,
 885             definition: Named("llvm.aarch64.neon.sshl.v2i32")
 886         },
 887         "shl_u32" => Intrinsic {
 888             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 889             output: &::U32x2,
 890             definition: Named("llvm.aarch64.neon.ushl.v2i32")
 891         },
 892         "shl_s64" => Intrinsic {
 893             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 894             output: &::I64x1,
 895             definition: Named("llvm.aarch64.neon.sshl.v1i64")
 896         },
 897         "shl_u64" => Intrinsic {
 898             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 899             output: &::U64x1,
 900             definition: Named("llvm.aarch64.neon.ushl.v1i64")
 901         },
 902         "shlq_s8" => Intrinsic {
 903             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 904             output: &::I8x16,
 905             definition: Named("llvm.aarch64.neon.sshl.v16i8")
 906         },
 907         "shlq_u8" => Intrinsic {
 908             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 909             output: &::U8x16,
 910             definition: Named("llvm.aarch64.neon.ushl.v16i8")
 911         },
 912         "shlq_s16" => Intrinsic {
 913             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 914             output: &::I16x8,
 915             definition: Named("llvm.aarch64.neon.sshl.v8i16")
 916         },
 917         "shlq_u16" => Intrinsic {
 918             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 919             output: &::U16x8,
 920             definition: Named("llvm.aarch64.neon.ushl.v8i16")
 921         },
 922         "shlq_s32" => Intrinsic {
 923             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
 924             output: &::I32x4,
 925             definition: Named("llvm.aarch64.neon.sshl.v4i32")
 926         },
 927         "shlq_u32" => Intrinsic {
 928             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
 929             output: &::U32x4,
 930             definition: Named("llvm.aarch64.neon.ushl.v4i32")
 931         },
 932         "shlq_s64" => Intrinsic {
 933             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
 934             output: &::I64x2,
 935             definition: Named("llvm.aarch64.neon.sshl.v2i64")
 936         },
 937         "shlq_u64" => Intrinsic {
 938             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
 939             output: &::U64x2,
 940             definition: Named("llvm.aarch64.neon.ushl.v2i64")
 941         },
 942         "qshl_s8" => Intrinsic {
 943             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
 944             output: &::I8x8,
 945             definition: Named("llvm.aarch64.neon.sqshl.v8i8")
 946         },
 947         "qshl_u8" => Intrinsic {
 948             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
 949             output: &::U8x8,
 950             definition: Named("llvm.aarch64.neon.uqshl.v8i8")
 951         },
 952         "qshl_s16" => Intrinsic {
 953             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
 954             output: &::I16x4,
 955             definition: Named("llvm.aarch64.neon.sqshl.v4i16")
 956         },
 957         "qshl_u16" => Intrinsic {
 958             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
 959             output: &::U16x4,
 960             definition: Named("llvm.aarch64.neon.uqshl.v4i16")
 961         },
 962         "qshl_s32" => Intrinsic {
 963             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
 964             output: &::I32x2,
 965             definition: Named("llvm.aarch64.neon.sqshl.v2i32")
 966         },
 967         "qshl_u32" => Intrinsic {
 968             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
 969             output: &::U32x2,
 970             definition: Named("llvm.aarch64.neon.uqshl.v2i32")
 971         },
 972         "qshl_s64" => Intrinsic {
 973             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
 974             output: &::I64x1,
 975             definition: Named("llvm.aarch64.neon.sqshl.v1i64")
 976         },
 977         "qshl_u64" => Intrinsic {
 978             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
 979             output: &::U64x1,
 980             definition: Named("llvm.aarch64.neon.uqshl.v1i64")
 981         },
 982         "qshlq_s8" => Intrinsic {
 983             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
 984             output: &::I8x16,
 985             definition: Named("llvm.aarch64.neon.sqshl.v16i8")
 986         },
 987         "qshlq_u8" => Intrinsic {
 988             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
 989             output: &::U8x16,
 990             definition: Named("llvm.aarch64.neon.uqshl.v16i8")
 991         },
 992         "qshlq_s16" => Intrinsic {
 993             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
 994             output: &::I16x8,
 995             definition: Named("llvm.aarch64.neon.sqshl.v8i16")
 996         },
 997         "qshlq_u16" => Intrinsic {
 998             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
 999             output: &::U16x8,
1000             definition: Named("llvm.aarch64.neon.uqshl.v8i16")
1001         },
1002         "qshlq_s32" => Intrinsic {
1003             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1004             output: &::I32x4,
1005             definition: Named("llvm.aarch64.neon.sqshl.v4i32")
1006         },
1007         "qshlq_u32" => Intrinsic {
1008             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1009             output: &::U32x4,
1010             definition: Named("llvm.aarch64.neon.uqshl.v4i32")
1011         },
1012         "qshlq_s64" => Intrinsic {
1013             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1014             output: &::I64x2,
1015             definition: Named("llvm.aarch64.neon.sqshl.v2i64")
1016         },
1017         "qshlq_u64" => Intrinsic {
1018             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1019             output: &::U64x2,
1020             definition: Named("llvm.aarch64.neon.uqshl.v2i64")
1021         },
1022         "rshl_s8" => Intrinsic {
1023             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1024             output: &::I8x8,
1025             definition: Named("llvm.aarch64.neon.srshl.v8i8")
1026         },
1027         "rshl_u8" => Intrinsic {
1028             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1029             output: &::U8x8,
1030             definition: Named("llvm.aarch64.neon.urshl.v8i8")
1031         },
1032         "rshl_s16" => Intrinsic {
1033             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1034             output: &::I16x4,
1035             definition: Named("llvm.aarch64.neon.srshl.v4i16")
1036         },
1037         "rshl_u16" => Intrinsic {
1038             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1039             output: &::U16x4,
1040             definition: Named("llvm.aarch64.neon.urshl.v4i16")
1041         },
1042         "rshl_s32" => Intrinsic {
1043             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1044             output: &::I32x2,
1045             definition: Named("llvm.aarch64.neon.srshl.v2i32")
1046         },
1047         "rshl_u32" => Intrinsic {
1048             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1049             output: &::U32x2,
1050             definition: Named("llvm.aarch64.neon.urshl.v2i32")
1051         },
1052         "rshl_s64" => Intrinsic {
1053             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1054             output: &::I64x1,
1055             definition: Named("llvm.aarch64.neon.srshl.v1i64")
1056         },
1057         "rshl_u64" => Intrinsic {
1058             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1059             output: &::U64x1,
1060             definition: Named("llvm.aarch64.neon.urshl.v1i64")
1061         },
1062         "rshlq_s8" => Intrinsic {
1063             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1064             output: &::I8x16,
1065             definition: Named("llvm.aarch64.neon.srshl.v16i8")
1066         },
1067         "rshlq_u8" => Intrinsic {
1068             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1069             output: &::U8x16,
1070             definition: Named("llvm.aarch64.neon.urshl.v16i8")
1071         },
1072         "rshlq_s16" => Intrinsic {
1073             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1074             output: &::I16x8,
1075             definition: Named("llvm.aarch64.neon.srshl.v8i16")
1076         },
1077         "rshlq_u16" => Intrinsic {
1078             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1079             output: &::U16x8,
1080             definition: Named("llvm.aarch64.neon.urshl.v8i16")
1081         },
1082         "rshlq_s32" => Intrinsic {
1083             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1084             output: &::I32x4,
1085             definition: Named("llvm.aarch64.neon.srshl.v4i32")
1086         },
1087         "rshlq_u32" => Intrinsic {
1088             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1089             output: &::U32x4,
1090             definition: Named("llvm.aarch64.neon.urshl.v4i32")
1091         },
1092         "rshlq_s64" => Intrinsic {
1093             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1094             output: &::I64x2,
1095             definition: Named("llvm.aarch64.neon.srshl.v2i64")
1096         },
1097         "rshlq_u64" => Intrinsic {
1098             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1099             output: &::U64x2,
1100             definition: Named("llvm.aarch64.neon.urshl.v2i64")
1101         },
1102         "qrshl_s8" => Intrinsic {
1103             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1104             output: &::I8x8,
1105             definition: Named("llvm.aarch64.neon.sqrshl.v8i8")
1106         },
1107         "qrshl_u8" => Intrinsic {
1108             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1109             output: &::U8x8,
1110             definition: Named("llvm.aarch64.neon.uqrshl.v8i8")
1111         },
1112         "qrshl_s16" => Intrinsic {
1113             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1114             output: &::I16x4,
1115             definition: Named("llvm.aarch64.neon.sqrshl.v4i16")
1116         },
1117         "qrshl_u16" => Intrinsic {
1118             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1119             output: &::U16x4,
1120             definition: Named("llvm.aarch64.neon.uqrshl.v4i16")
1121         },
1122         "qrshl_s32" => Intrinsic {
1123             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1124             output: &::I32x2,
1125             definition: Named("llvm.aarch64.neon.sqrshl.v2i32")
1126         },
1127         "qrshl_u32" => Intrinsic {
1128             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1129             output: &::U32x2,
1130             definition: Named("llvm.aarch64.neon.uqrshl.v2i32")
1131         },
1132         "qrshl_s64" => Intrinsic {
1133             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1134             output: &::I64x1,
1135             definition: Named("llvm.aarch64.neon.sqrshl.v1i64")
1136         },
1137         "qrshl_u64" => Intrinsic {
1138             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1139             output: &::U64x1,
1140             definition: Named("llvm.aarch64.neon.uqrshl.v1i64")
1141         },
1142         "qrshlq_s8" => Intrinsic {
1143             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1144             output: &::I8x16,
1145             definition: Named("llvm.aarch64.neon.sqrshl.v16i8")
1146         },
1147         "qrshlq_u8" => Intrinsic {
1148             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1149             output: &::U8x16,
1150             definition: Named("llvm.aarch64.neon.uqrshl.v16i8")
1151         },
1152         "qrshlq_s16" => Intrinsic {
1153             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1154             output: &::I16x8,
1155             definition: Named("llvm.aarch64.neon.sqrshl.v8i16")
1156         },
1157         "qrshlq_u16" => Intrinsic {
1158             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1159             output: &::U16x8,
1160             definition: Named("llvm.aarch64.neon.uqrshl.v8i16")
1161         },
1162         "qrshlq_s32" => Intrinsic {
1163             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1164             output: &::I32x4,
1165             definition: Named("llvm.aarch64.neon.sqrshl.v4i32")
1166         },
1167         "qrshlq_u32" => Intrinsic {
1168             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1169             output: &::U32x4,
1170             definition: Named("llvm.aarch64.neon.uqrshl.v4i32")
1171         },
1172         "qrshlq_s64" => Intrinsic {
1173             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1174             output: &::I64x2,
1175             definition: Named("llvm.aarch64.neon.sqrshl.v2i64")
1176         },
1177         "qrshlq_u64" => Intrinsic {
1178             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1179             output: &::U64x2,
1180             definition: Named("llvm.aarch64.neon.uqrshl.v2i64")
1181         },
1182         "qshrun_n_s16" => Intrinsic {
1183             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1184             output: &::I8x8,
1185             definition: Named("llvm.aarch64.neon.sqshrun.v8i8")
1186         },
1187         "qshrun_n_s32" => Intrinsic {
1188             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1189             output: &::I16x4,
1190             definition: Named("llvm.aarch64.neon.sqshrun.v4i16")
1191         },
1192         "qshrun_n_s64" => Intrinsic {
1193             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1194             output: &::I32x2,
1195             definition: Named("llvm.aarch64.neon.sqshrun.v2i32")
1196         },
1197         "qrshrun_n_s16" => Intrinsic {
1198             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1199             output: &::I8x8,
1200             definition: Named("llvm.aarch64.neon.sqrshrun.v8i8")
1201         },
1202         "qrshrun_n_s32" => Intrinsic {
1203             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1204             output: &::I16x4,
1205             definition: Named("llvm.aarch64.neon.sqrshrun.v4i16")
1206         },
1207         "qrshrun_n_s64" => Intrinsic {
1208             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1209             output: &::I32x2,
1210             definition: Named("llvm.aarch64.neon.sqrshrun.v2i32")
1211         },
1212         "qshrn_n_s16" => Intrinsic {
1213             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1214             output: &::I8x8,
1215             definition: Named("llvm.aarch64.neon.sqshrn.v8i8")
1216         },
1217         "qshrn_n_u16" => Intrinsic {
1218             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1219             output: &::U8x8,
1220             definition: Named("llvm.aarch64.neon.uqshrn.v8i8")
1221         },
1222         "qshrn_n_s32" => Intrinsic {
1223             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1224             output: &::I16x4,
1225             definition: Named("llvm.aarch64.neon.sqshrn.v4i16")
1226         },
1227         "qshrn_n_u32" => Intrinsic {
1228             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1229             output: &::U16x4,
1230             definition: Named("llvm.aarch64.neon.uqshrn.v4i16")
1231         },
1232         "qshrn_n_s64" => Intrinsic {
1233             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1234             output: &::I32x2,
1235             definition: Named("llvm.aarch64.neon.sqshrn.v2i32")
1236         },
1237         "qshrn_n_u64" => Intrinsic {
1238             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1239             output: &::U32x2,
1240             definition: Named("llvm.aarch64.neon.uqshrn.v2i32")
1241         },
1242         "rshrn_n_s16" => Intrinsic {
1243             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1244             output: &::I8x8,
1245             definition: Named("llvm.aarch64.neon.rshrn.v8i8")
1246         },
1247         "rshrn_n_u16" => Intrinsic {
1248             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1249             output: &::U8x8,
1250             definition: Named("llvm.aarch64.neon.rshrn.v8i8")
1251         },
1252         "rshrn_n_s32" => Intrinsic {
1253             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1254             output: &::I16x4,
1255             definition: Named("llvm.aarch64.neon.rshrn.v4i16")
1256         },
1257         "rshrn_n_u32" => Intrinsic {
1258             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1259             output: &::U16x4,
1260             definition: Named("llvm.aarch64.neon.rshrn.v4i16")
1261         },
1262         "rshrn_n_s64" => Intrinsic {
1263             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1264             output: &::I32x2,
1265             definition: Named("llvm.aarch64.neon.rshrn.v2i32")
1266         },
1267         "rshrn_n_u64" => Intrinsic {
1268             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1269             output: &::U32x2,
1270             definition: Named("llvm.aarch64.neon.rshrn.v2i32")
1271         },
1272         "qrshrn_n_s16" => Intrinsic {
1273             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1274             output: &::I8x8,
1275             definition: Named("llvm.aarch64.neon.sqrshrn.v8i8")
1276         },
1277         "qrshrn_n_u16" => Intrinsic {
1278             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1279             output: &::U8x8,
1280             definition: Named("llvm.aarch64.neon.uqrshrn.v8i8")
1281         },
1282         "qrshrn_n_s32" => Intrinsic {
1283             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1284             output: &::I16x4,
1285             definition: Named("llvm.aarch64.neon.sqrshrn.v4i16")
1286         },
1287         "qrshrn_n_u32" => Intrinsic {
1288             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1289             output: &::U16x4,
1290             definition: Named("llvm.aarch64.neon.uqrshrn.v4i16")
1291         },
1292         "qrshrn_n_s64" => Intrinsic {
1293             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1294             output: &::I32x2,
1295             definition: Named("llvm.aarch64.neon.sqrshrn.v2i32")
1296         },
1297         "qrshrn_n_u64" => Intrinsic {
1298             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1299             output: &::U32x2,
1300             definition: Named("llvm.aarch64.neon.uqrshrn.v2i32")
1301         },
1302         "sri_s8" => Intrinsic {
1303             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1304             output: &::I8x8,
1305             definition: Named("llvm.aarch64.neon.vsri.v8i8")
1306         },
1307         "sri_u8" => Intrinsic {
1308             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1309             output: &::U8x8,
1310             definition: Named("llvm.aarch64.neon.vsri.v8i8")
1311         },
1312         "sri_s16" => Intrinsic {
1313             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1314             output: &::I16x4,
1315             definition: Named("llvm.aarch64.neon.vsri.v4i16")
1316         },
1317         "sri_u16" => Intrinsic {
1318             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1319             output: &::U16x4,
1320             definition: Named("llvm.aarch64.neon.vsri.v4i16")
1321         },
1322         "sri_s32" => Intrinsic {
1323             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1324             output: &::I32x2,
1325             definition: Named("llvm.aarch64.neon.vsri.v2i32")
1326         },
1327         "sri_u32" => Intrinsic {
1328             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1329             output: &::U32x2,
1330             definition: Named("llvm.aarch64.neon.vsri.v2i32")
1331         },
1332         "sri_s64" => Intrinsic {
1333             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1334             output: &::I64x1,
1335             definition: Named("llvm.aarch64.neon.vsri.v1i64")
1336         },
1337         "sri_u64" => Intrinsic {
1338             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1339             output: &::U64x1,
1340             definition: Named("llvm.aarch64.neon.vsri.v1i64")
1341         },
1342         "sriq_s8" => Intrinsic {
1343             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1344             output: &::I8x16,
1345             definition: Named("llvm.aarch64.neon.vsri.v16i8")
1346         },
1347         "sriq_u8" => Intrinsic {
1348             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1349             output: &::U8x16,
1350             definition: Named("llvm.aarch64.neon.vsri.v16i8")
1351         },
1352         "sriq_s16" => Intrinsic {
1353             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1354             output: &::I16x8,
1355             definition: Named("llvm.aarch64.neon.vsri.v8i16")
1356         },
1357         "sriq_u16" => Intrinsic {
1358             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1359             output: &::U16x8,
1360             definition: Named("llvm.aarch64.neon.vsri.v8i16")
1361         },
1362         "sriq_s32" => Intrinsic {
1363             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1364             output: &::I32x4,
1365             definition: Named("llvm.aarch64.neon.vsri.v4i32")
1366         },
1367         "sriq_u32" => Intrinsic {
1368             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1369             output: &::U32x4,
1370             definition: Named("llvm.aarch64.neon.vsri.v4i32")
1371         },
1372         "sriq_s64" => Intrinsic {
1373             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1374             output: &::I64x2,
1375             definition: Named("llvm.aarch64.neon.vsri.v2i64")
1376         },
1377         "sriq_u64" => Intrinsic {
1378             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1379             output: &::U64x2,
1380             definition: Named("llvm.aarch64.neon.vsri.v2i64")
1381         },
1382         "sli_s8" => Intrinsic {
1383             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1384             output: &::I8x8,
1385             definition: Named("llvm.aarch64.neon.vsli.v8i8")
1386         },
1387         "sli_u8" => Intrinsic {
1388             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1389             output: &::U8x8,
1390             definition: Named("llvm.aarch64.neon.vsli.v8i8")
1391         },
1392         "sli_s16" => Intrinsic {
1393             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1394             output: &::I16x4,
1395             definition: Named("llvm.aarch64.neon.vsli.v4i16")
1396         },
1397         "sli_u16" => Intrinsic {
1398             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1399             output: &::U16x4,
1400             definition: Named("llvm.aarch64.neon.vsli.v4i16")
1401         },
1402         "sli_s32" => Intrinsic {
1403             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1404             output: &::I32x2,
1405             definition: Named("llvm.aarch64.neon.vsli.v2i32")
1406         },
1407         "sli_u32" => Intrinsic {
1408             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1409             output: &::U32x2,
1410             definition: Named("llvm.aarch64.neon.vsli.v2i32")
1411         },
1412         "sli_s64" => Intrinsic {
1413             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1414             output: &::I64x1,
1415             definition: Named("llvm.aarch64.neon.vsli.v1i64")
1416         },
1417         "sli_u64" => Intrinsic {
1418             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1419             output: &::U64x1,
1420             definition: Named("llvm.aarch64.neon.vsli.v1i64")
1421         },
1422         "sliq_s8" => Intrinsic {
1423             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1424             output: &::I8x16,
1425             definition: Named("llvm.aarch64.neon.vsli.v16i8")
1426         },
1427         "sliq_u8" => Intrinsic {
1428             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1429             output: &::U8x16,
1430             definition: Named("llvm.aarch64.neon.vsli.v16i8")
1431         },
1432         "sliq_s16" => Intrinsic {
1433             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1434             output: &::I16x8,
1435             definition: Named("llvm.aarch64.neon.vsli.v8i16")
1436         },
1437         "sliq_u16" => Intrinsic {
1438             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1439             output: &::U16x8,
1440             definition: Named("llvm.aarch64.neon.vsli.v8i16")
1441         },
1442         "sliq_s32" => Intrinsic {
1443             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1444             output: &::I32x4,
1445             definition: Named("llvm.aarch64.neon.vsli.v4i32")
1446         },
1447         "sliq_u32" => Intrinsic {
1448             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1449             output: &::U32x4,
1450             definition: Named("llvm.aarch64.neon.vsli.v4i32")
1451         },
1452         "sliq_s64" => Intrinsic {
1453             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1454             output: &::I64x2,
1455             definition: Named("llvm.aarch64.neon.vsli.v2i64")
1456         },
1457         "sliq_u64" => Intrinsic {
1458             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1459             output: &::U64x2,
1460             definition: Named("llvm.aarch64.neon.vsli.v2i64")
1461         },
1462         "vqmovn_s16" => Intrinsic {
1463             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1464             output: &::I8x8,
1465             definition: Named("llvm.aarch64.neon.sqxtn.v8i8")
1466         },
1467         "vqmovn_u16" => Intrinsic {
1468             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1469             output: &::U8x8,
1470             definition: Named("llvm.aarch64.neon.uqxtn.v8i8")
1471         },
1472         "vqmovn_s32" => Intrinsic {
1473             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1474             output: &::I16x4,
1475             definition: Named("llvm.aarch64.neon.sqxtn.v4i16")
1476         },
1477         "vqmovn_u32" => Intrinsic {
1478             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1479             output: &::U16x4,
1480             definition: Named("llvm.aarch64.neon.uqxtn.v4i16")
1481         },
1482         "vqmovn_s64" => Intrinsic {
1483             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1484             output: &::I32x2,
1485             definition: Named("llvm.aarch64.neon.sqxtn.v2i32")
1486         },
1487         "vqmovn_u64" => Intrinsic {
1488             inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
1489             output: &::U32x2,
1490             definition: Named("llvm.aarch64.neon.uqxtn.v2i32")
1491         },
1492         "abs_s8" => Intrinsic {
1493             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1494             output: &::I8x8,
1495             definition: Named("llvm.aarch64.neon.abs.v8i8")
1496         },
1497         "abs_s16" => Intrinsic {
1498             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1499             output: &::I16x4,
1500             definition: Named("llvm.aarch64.neon.abs.v4i16")
1501         },
1502         "abs_s32" => Intrinsic {
1503             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1504             output: &::I32x2,
1505             definition: Named("llvm.aarch64.neon.abs.v2i32")
1506         },
1507         "abs_s64" => Intrinsic {
1508             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1509             output: &::I64x1,
1510             definition: Named("llvm.aarch64.neon.abs.v1i64")
1511         },
1512         "absq_s8" => Intrinsic {
1513             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1514             output: &::I8x16,
1515             definition: Named("llvm.aarch64.neon.abs.v16i8")
1516         },
1517         "absq_s16" => Intrinsic {
1518             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1519             output: &::I16x8,
1520             definition: Named("llvm.aarch64.neon.abs.v8i16")
1521         },
1522         "absq_s32" => Intrinsic {
1523             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1524             output: &::I32x4,
1525             definition: Named("llvm.aarch64.neon.abs.v4i32")
1526         },
1527         "absq_s64" => Intrinsic {
1528             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1529             output: &::I64x2,
1530             definition: Named("llvm.aarch64.neon.abs.v2i64")
1531         },
1532         "abs_f32" => Intrinsic {
1533             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1534             output: &::F32x2,
1535             definition: Named("llvm.fabs.v2f32")
1536         },
1537         "abs_f64" => Intrinsic {
1538             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1539             output: &::F64x1,
1540             definition: Named("llvm.fabs.v1f64")
1541         },
1542         "absq_f32" => Intrinsic {
1543             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1544             output: &::F32x4,
1545             definition: Named("llvm.fabs.v4f32")
1546         },
1547         "absq_f64" => Intrinsic {
1548             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1549             output: &::F64x2,
1550             definition: Named("llvm.fabs.v2f64")
1551         },
1552         "qabs_s8" => Intrinsic {
1553             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1554             output: &::I8x8,
1555             definition: Named("llvm.aarch64.neon.sqabs.v8i8")
1556         },
1557         "qabs_s16" => Intrinsic {
1558             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1559             output: &::I16x4,
1560             definition: Named("llvm.aarch64.neon.sqabs.v4i16")
1561         },
1562         "qabs_s32" => Intrinsic {
1563             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1564             output: &::I32x2,
1565             definition: Named("llvm.aarch64.neon.sqabs.v2i32")
1566         },
1567         "qabs_s64" => Intrinsic {
1568             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1569             output: &::I64x1,
1570             definition: Named("llvm.aarch64.neon.sqabs.v1i64")
1571         },
1572         "qabsq_s8" => Intrinsic {
1573             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1574             output: &::I8x16,
1575             definition: Named("llvm.aarch64.neon.sqabs.v16i8")
1576         },
1577         "qabsq_s16" => Intrinsic {
1578             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1579             output: &::I16x8,
1580             definition: Named("llvm.aarch64.neon.sqabs.v8i16")
1581         },
1582         "qabsq_s32" => Intrinsic {
1583             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1584             output: &::I32x4,
1585             definition: Named("llvm.aarch64.neon.sqabs.v4i32")
1586         },
1587         "qabsq_s64" => Intrinsic {
1588             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1589             output: &::I64x2,
1590             definition: Named("llvm.aarch64.neon.sqabs.v2i64")
1591         },
1592         "qneg_s8" => Intrinsic {
1593             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1594             output: &::I8x8,
1595             definition: Named("llvm.aarch64.neon.sqneg.v8i8")
1596         },
1597         "qneg_s16" => Intrinsic {
1598             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1599             output: &::I16x4,
1600             definition: Named("llvm.aarch64.neon.sqneg.v4i16")
1601         },
1602         "qneg_s32" => Intrinsic {
1603             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1604             output: &::I32x2,
1605             definition: Named("llvm.aarch64.neon.sqneg.v2i32")
1606         },
1607         "qneg_s64" => Intrinsic {
1608             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS },
1609             output: &::I64x1,
1610             definition: Named("llvm.aarch64.neon.sqneg.v1i64")
1611         },
1612         "qnegq_s8" => Intrinsic {
1613             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1614             output: &::I8x16,
1615             definition: Named("llvm.aarch64.neon.sqneg.v16i8")
1616         },
1617         "qnegq_s16" => Intrinsic {
1618             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1619             output: &::I16x8,
1620             definition: Named("llvm.aarch64.neon.sqneg.v8i16")
1621         },
1622         "qnegq_s32" => Intrinsic {
1623             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1624             output: &::I32x4,
1625             definition: Named("llvm.aarch64.neon.sqneg.v4i32")
1626         },
1627         "qnegq_s64" => Intrinsic {
1628             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1629             output: &::I64x2,
1630             definition: Named("llvm.aarch64.neon.sqneg.v2i64")
1631         },
1632         "clz_s8" => Intrinsic {
1633             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1634             output: &::I8x8,
1635             definition: Named("llvm.ctlz.v8i8")
1636         },
1637         "clz_u8" => Intrinsic {
1638             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1639             output: &::U8x8,
1640             definition: Named("llvm.ctlz.v8i8")
1641         },
1642         "clz_s16" => Intrinsic {
1643             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1644             output: &::I16x4,
1645             definition: Named("llvm.ctlz.v4i16")
1646         },
1647         "clz_u16" => Intrinsic {
1648             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1649             output: &::U16x4,
1650             definition: Named("llvm.ctlz.v4i16")
1651         },
1652         "clz_s32" => Intrinsic {
1653             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1654             output: &::I32x2,
1655             definition: Named("llvm.ctlz.v2i32")
1656         },
1657         "clz_u32" => Intrinsic {
1658             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1659             output: &::U32x2,
1660             definition: Named("llvm.ctlz.v2i32")
1661         },
1662         "clzq_s8" => Intrinsic {
1663             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1664             output: &::I8x16,
1665             definition: Named("llvm.ctlz.v16i8")
1666         },
1667         "clzq_u8" => Intrinsic {
1668             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1669             output: &::U8x16,
1670             definition: Named("llvm.ctlz.v16i8")
1671         },
1672         "clzq_s16" => Intrinsic {
1673             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1674             output: &::I16x8,
1675             definition: Named("llvm.ctlz.v8i16")
1676         },
1677         "clzq_u16" => Intrinsic {
1678             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1679             output: &::U16x8,
1680             definition: Named("llvm.ctlz.v8i16")
1681         },
1682         "clzq_s32" => Intrinsic {
1683             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1684             output: &::I32x4,
1685             definition: Named("llvm.ctlz.v4i32")
1686         },
1687         "clzq_u32" => Intrinsic {
1688             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1689             output: &::U32x4,
1690             definition: Named("llvm.ctlz.v4i32")
1691         },
1692         "cls_s8" => Intrinsic {
1693             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1694             output: &::I8x8,
1695             definition: Named("llvm.aarch64.neon.cls.v8i8")
1696         },
1697         "cls_u8" => Intrinsic {
1698             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1699             output: &::U8x8,
1700             definition: Named("llvm.aarch64.neon.cls.v8i8")
1701         },
1702         "cls_s16" => Intrinsic {
1703             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1704             output: &::I16x4,
1705             definition: Named("llvm.aarch64.neon.cls.v4i16")
1706         },
1707         "cls_u16" => Intrinsic {
1708             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1709             output: &::U16x4,
1710             definition: Named("llvm.aarch64.neon.cls.v4i16")
1711         },
1712         "cls_s32" => Intrinsic {
1713             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1714             output: &::I32x2,
1715             definition: Named("llvm.aarch64.neon.cls.v2i32")
1716         },
1717         "cls_u32" => Intrinsic {
1718             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1719             output: &::U32x2,
1720             definition: Named("llvm.aarch64.neon.cls.v2i32")
1721         },
1722         "clsq_s8" => Intrinsic {
1723             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1724             output: &::I8x16,
1725             definition: Named("llvm.aarch64.neon.cls.v16i8")
1726         },
1727         "clsq_u8" => Intrinsic {
1728             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1729             output: &::U8x16,
1730             definition: Named("llvm.aarch64.neon.cls.v16i8")
1731         },
1732         "clsq_s16" => Intrinsic {
1733             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1734             output: &::I16x8,
1735             definition: Named("llvm.aarch64.neon.cls.v8i16")
1736         },
1737         "clsq_u16" => Intrinsic {
1738             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1739             output: &::U16x8,
1740             definition: Named("llvm.aarch64.neon.cls.v8i16")
1741         },
1742         "clsq_s32" => Intrinsic {
1743             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1744             output: &::I32x4,
1745             definition: Named("llvm.aarch64.neon.cls.v4i32")
1746         },
1747         "clsq_u32" => Intrinsic {
1748             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1749             output: &::U32x4,
1750             definition: Named("llvm.aarch64.neon.cls.v4i32")
1751         },
1752         "cnt_s8" => Intrinsic {
1753             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1754             output: &::I8x8,
1755             definition: Named("llvm.ctpop.v8i8")
1756         },
1757         "cnt_u8" => Intrinsic {
1758             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1759             output: &::U8x8,
1760             definition: Named("llvm.ctpop.v8i8")
1761         },
1762         "cntq_s8" => Intrinsic {
1763             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1764             output: &::I8x16,
1765             definition: Named("llvm.ctpop.v16i8")
1766         },
1767         "cntq_u8" => Intrinsic {
1768             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1769             output: &::U8x16,
1770             definition: Named("llvm.ctpop.v16i8")
1771         },
1772         "recpe_u32" => Intrinsic {
1773             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1774             output: &::U32x2,
1775             definition: Named("llvm.aarch64.neon.urecpe.v2i32")
1776         },
1777         "recpe_f32" => Intrinsic {
1778             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1779             output: &::F32x2,
1780             definition: Named("llvm.aarch64.neon.frecpe.v2f32")
1781         },
1782         "recpe_f64" => Intrinsic {
1783             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1784             output: &::F64x1,
1785             definition: Named("llvm.aarch64.neon.frecpe.v1f64")
1786         },
1787         "recpeq_u32" => Intrinsic {
1788             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1789             output: &::U32x4,
1790             definition: Named("llvm.aarch64.neon.urecpe.v4i32")
1791         },
1792         "recpeq_f32" => Intrinsic {
1793             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1794             output: &::F32x4,
1795             definition: Named("llvm.aarch64.neon.frecpe.v4f32")
1796         },
1797         "recpeq_f64" => Intrinsic {
1798             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1799             output: &::F64x2,
1800             definition: Named("llvm.aarch64.neon.frecpe.v2f64")
1801         },
1802         "recps_f32" => Intrinsic {
1803             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1804             output: &::F32x2,
1805             definition: Named("llvm.aarch64.neon.frecps.v2f32")
1806         },
1807         "recps_f64" => Intrinsic {
1808             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
1809             output: &::F64x1,
1810             definition: Named("llvm.aarch64.neon.frecps.v1f64")
1811         },
1812         "recpsq_f32" => Intrinsic {
1813             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1814             output: &::F32x4,
1815             definition: Named("llvm.aarch64.neon.frecps.v4f32")
1816         },
1817         "recpsq_f64" => Intrinsic {
1818             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
1819             output: &::F64x2,
1820             definition: Named("llvm.aarch64.neon.frecps.v2f64")
1821         },
1822         "sqrt_f32" => Intrinsic {
1823             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1824             output: &::F32x2,
1825             definition: Named("llvm.sqrt.v2f32")
1826         },
1827         "sqrt_f64" => Intrinsic {
1828             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1829             output: &::F64x1,
1830             definition: Named("llvm.sqrt.v1f64")
1831         },
1832         "sqrtq_f32" => Intrinsic {
1833             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1834             output: &::F32x4,
1835             definition: Named("llvm.sqrt.v4f32")
1836         },
1837         "sqrtq_f64" => Intrinsic {
1838             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1839             output: &::F64x2,
1840             definition: Named("llvm.sqrt.v2f64")
1841         },
1842         "rsqrte_u32" => Intrinsic {
1843             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1844             output: &::U32x2,
1845             definition: Named("llvm.aarch64.neon.ursqrte.v2i32")
1846         },
1847         "rsqrte_f32" => Intrinsic {
1848             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1849             output: &::F32x2,
1850             definition: Named("llvm.aarch64.neon.frsqrte.v2f32")
1851         },
1852         "rsqrte_f64" => Intrinsic {
1853             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS },
1854             output: &::F64x1,
1855             definition: Named("llvm.aarch64.neon.frsqrte.v1f64")
1856         },
1857         "rsqrteq_u32" => Intrinsic {
1858             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1859             output: &::U32x4,
1860             definition: Named("llvm.aarch64.neon.ursqrte.v4i32")
1861         },
1862         "rsqrteq_f32" => Intrinsic {
1863             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1864             output: &::F32x4,
1865             definition: Named("llvm.aarch64.neon.frsqrte.v4f32")
1866         },
1867         "rsqrteq_f64" => Intrinsic {
1868             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
1869             output: &::F64x2,
1870             definition: Named("llvm.aarch64.neon.frsqrte.v2f64")
1871         },
1872         "rsqrts_f32" => Intrinsic {
1873             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1874             output: &::F32x2,
1875             definition: Named("llvm.aarch64.neon.frsqrts.v2f32")
1876         },
1877         "rsqrts_f64" => Intrinsic {
1878             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS },
1879             output: &::F64x1,
1880             definition: Named("llvm.aarch64.neon.frsqrts.v1f64")
1881         },
1882         "rsqrtsq_f32" => Intrinsic {
1883             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1884             output: &::F32x4,
1885             definition: Named("llvm.aarch64.neon.frsqrts.v4f32")
1886         },
1887         "rsqrtsq_f64" => Intrinsic {
1888             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
1889             output: &::F64x2,
1890             definition: Named("llvm.aarch64.neon.frsqrts.v2f64")
1891         },
1892         "rbit_s8" => Intrinsic {
1893             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1894             output: &::I8x8,
1895             definition: Named("llvm.aarch64.neon.rbit.v8i8")
1896         },
1897         "rbit_u8" => Intrinsic {
1898             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1899             output: &::U8x8,
1900             definition: Named("llvm.aarch64.neon.rbit.v8i8")
1901         },
1902         "rbitq_s8" => Intrinsic {
1903             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1904             output: &::I8x16,
1905             definition: Named("llvm.aarch64.neon.rbit.v16i8")
1906         },
1907         "rbitq_u8" => Intrinsic {
1908             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1909             output: &::U8x16,
1910             definition: Named("llvm.aarch64.neon.rbit.v16i8")
1911         },
1912         "ld2_s8" => Intrinsic {
1913             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
1914             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG },
1915             definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1916         },
1917         "ld2_u8" => Intrinsic {
1918             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
1919             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG },
1920             definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1921         },
1922         "ld2_s16" => Intrinsic {
1923             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
1924             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG },
1925             definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1926         },
1927         "ld2_u16" => Intrinsic {
1928             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
1929             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG },
1930             definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1931         },
1932         "ld2_s32" => Intrinsic {
1933             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
1934             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG },
1935             definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1936         },
1937         "ld2_u32" => Intrinsic {
1938             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
1939             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG },
1940             definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1941         },
1942         "ld2_s64" => Intrinsic {
1943             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
1944             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG },
1945             definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1946         },
1947         "ld2_u64" => Intrinsic {
1948             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
1949             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG },
1950             definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1951         },
1952         "ld2_f32" => Intrinsic {
1953             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
1954             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG },
1955             definition: Named("llvm.aarch64.neon.ld2.v2f32.p0v2f32")
1956         },
1957         "ld2_f64" => Intrinsic {
1958             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
1959             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG },
1960             definition: Named("llvm.aarch64.neon.ld2.v1f64.p0v1f64")
1961         },
1962         "ld2q_s8" => Intrinsic {
1963             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
1964             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG },
1965             definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1966         },
1967         "ld2q_u8" => Intrinsic {
1968             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
1969             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG },
1970             definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1971         },
1972         "ld2q_s16" => Intrinsic {
1973             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
1974             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG },
1975             definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1976         },
1977         "ld2q_u16" => Intrinsic {
1978             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
1979             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG },
1980             definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1981         },
1982         "ld2q_s32" => Intrinsic {
1983             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
1984             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG },
1985             definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1986         },
1987         "ld2q_u32" => Intrinsic {
1988             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
1989             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG },
1990             definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1991         },
1992         "ld2q_s64" => Intrinsic {
1993             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
1994             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG },
1995             definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
1996         },
1997         "ld2q_u64" => Intrinsic {
1998             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
1999             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG },
2000             definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
2001         },
2002         "ld2q_f32" => Intrinsic {
2003             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2004             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG },
2005             definition: Named("llvm.aarch64.neon.ld2.v4f32.p0v4f32")
2006         },
2007         "ld2q_f64" => Intrinsic {
2008             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2009             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG },
2010             definition: Named("llvm.aarch64.neon.ld2.v2f64.p0v2f64")
2011         },
2012         "ld3_s8" => Intrinsic {
2013             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
2014             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2015             definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2016         },
2017         "ld3_u8" => Intrinsic {
2018             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
2019             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2020             definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2021         },
2022         "ld3_s16" => Intrinsic {
2023             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
2024             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2025             definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2026         },
2027         "ld3_u16" => Intrinsic {
2028             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
2029             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2030             definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2031         },
2032         "ld3_s32" => Intrinsic {
2033             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
2034             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2035             definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2036         },
2037         "ld3_u32" => Intrinsic {
2038             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
2039             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2040             definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2041         },
2042         "ld3_s64" => Intrinsic {
2043             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
2044             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2045             definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2046         },
2047         "ld3_u64" => Intrinsic {
2048             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
2049             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2050             definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2051         },
2052         "ld3_f32" => Intrinsic {
2053             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
2054             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2055             definition: Named("llvm.aarch64.neon.ld3.v2f32.p0v2f32")
2056         },
2057         "ld3_f64" => Intrinsic {
2058             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
2059             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2060             definition: Named("llvm.aarch64.neon.ld3.v1f64.p0v1f64")
2061         },
2062         "ld3q_s8" => Intrinsic {
2063             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
2064             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2065             definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2066         },
2067         "ld3q_u8" => Intrinsic {
2068             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
2069             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2070             definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2071         },
2072         "ld3q_s16" => Intrinsic {
2073             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
2074             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2075             definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2076         },
2077         "ld3q_u16" => Intrinsic {
2078             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
2079             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2080             definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2081         },
2082         "ld3q_s32" => Intrinsic {
2083             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
2084             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2085             definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2086         },
2087         "ld3q_u32" => Intrinsic {
2088             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
2089             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2090             definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2091         },
2092         "ld3q_s64" => Intrinsic {
2093             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
2094             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2095             definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2096         },
2097         "ld3q_u64" => Intrinsic {
2098             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
2099             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2100             definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2101         },
2102         "ld3q_f32" => Intrinsic {
2103             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2104             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2105             definition: Named("llvm.aarch64.neon.ld3.v4f32.p0v4f32")
2106         },
2107         "ld3q_f64" => Intrinsic {
2108             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2109             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2110             definition: Named("llvm.aarch64.neon.ld3.v2f64.p0v2f64")
2111         },
2112         "ld4_s8" => Intrinsic {
2113             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS },
2114             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2115             definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2116         },
2117         "ld4_u8" => Intrinsic {
2118             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS },
2119             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2120             definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2121         },
2122         "ld4_s16" => Intrinsic {
2123             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS },
2124             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2125             definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2126         },
2127         "ld4_u16" => Intrinsic {
2128             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS },
2129             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2130             definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2131         },
2132         "ld4_s32" => Intrinsic {
2133             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS },
2134             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2135             definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2136         },
2137         "ld4_u32" => Intrinsic {
2138             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS },
2139             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2140             definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2141         },
2142         "ld4_s64" => Intrinsic {
2143             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS },
2144             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2145             definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2146         },
2147         "ld4_u64" => Intrinsic {
2148             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS },
2149             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2150             definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2151         },
2152         "ld4_f32" => Intrinsic {
2153             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS },
2154             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2155             definition: Named("llvm.aarch64.neon.ld4.v2f32.p0v2f32")
2156         },
2157         "ld4_f64" => Intrinsic {
2158             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS },
2159             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2160             definition: Named("llvm.aarch64.neon.ld4.v1f64.p0v1f64")
2161         },
2162         "ld4q_s8" => Intrinsic {
2163             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS },
2164             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2165             definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2166         },
2167         "ld4q_u8" => Intrinsic {
2168             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS },
2169             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2170             definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2171         },
2172         "ld4q_s16" => Intrinsic {
2173             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS },
2174             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2175             definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2176         },
2177         "ld4q_u16" => Intrinsic {
2178             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS },
2179             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2180             definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2181         },
2182         "ld4q_s32" => Intrinsic {
2183             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS },
2184             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2185             definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2186         },
2187         "ld4q_u32" => Intrinsic {
2188             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS },
2189             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2190             definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2191         },
2192         "ld4q_s64" => Intrinsic {
2193             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS },
2194             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2195             definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2196         },
2197         "ld4q_u64" => Intrinsic {
2198             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS },
2199             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2200             definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2201         },
2202         "ld4q_f32" => Intrinsic {
2203             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS },
2204             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2205             definition: Named("llvm.aarch64.neon.ld4.v4f32.p0v4f32")
2206         },
2207         "ld4q_f64" => Intrinsic {
2208             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS },
2209             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2210             definition: Named("llvm.aarch64.neon.ld4.v2f64.p0v2f64")
2211         },
2212         "ld2_dup_s8" => Intrinsic {
2213             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2214             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG },
2215             definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2216         },
2217         "ld2_dup_u8" => Intrinsic {
2218             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2219             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG },
2220             definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2221         },
2222         "ld2_dup_s16" => Intrinsic {
2223             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2224             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG },
2225             definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2226         },
2227         "ld2_dup_u16" => Intrinsic {
2228             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2229             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG },
2230             definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2231         },
2232         "ld2_dup_s32" => Intrinsic {
2233             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2234             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG },
2235             definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2236         },
2237         "ld2_dup_u32" => Intrinsic {
2238             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2239             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG },
2240             definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2241         },
2242         "ld2_dup_s64" => Intrinsic {
2243             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2244             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG },
2245             definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2246         },
2247         "ld2_dup_u64" => Intrinsic {
2248             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2249             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG },
2250             definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2251         },
2252         "ld2_dup_f32" => Intrinsic {
2253             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2254             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG },
2255             definition: Named("llvm.aarch64.neon.ld2.v2f32.p0f32")
2256         },
2257         "ld2_dup_f64" => Intrinsic {
2258             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2259             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG },
2260             definition: Named("llvm.aarch64.neon.ld2.v1f64.p0f64")
2261         },
2262         "ld2q_dup_s8" => Intrinsic {
2263             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2264             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG },
2265             definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2266         },
2267         "ld2q_dup_u8" => Intrinsic {
2268             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2269             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG },
2270             definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2271         },
2272         "ld2q_dup_s16" => Intrinsic {
2273             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2274             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG },
2275             definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2276         },
2277         "ld2q_dup_u16" => Intrinsic {
2278             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2279             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG },
2280             definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2281         },
2282         "ld2q_dup_s32" => Intrinsic {
2283             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2284             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG },
2285             definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2286         },
2287         "ld2q_dup_u32" => Intrinsic {
2288             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2289             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG },
2290             definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2291         },
2292         "ld2q_dup_s64" => Intrinsic {
2293             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2294             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG },
2295             definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2296         },
2297         "ld2q_dup_u64" => Intrinsic {
2298             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2299             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG },
2300             definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2301         },
2302         "ld2q_dup_f32" => Intrinsic {
2303             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2304             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG },
2305             definition: Named("llvm.aarch64.neon.ld2.v4f32.p0f32")
2306         },
2307         "ld2q_dup_f64" => Intrinsic {
2308             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2309             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG },
2310             definition: Named("llvm.aarch64.neon.ld2.v2f64.p0f64")
2311         },
2312         "ld3_dup_s8" => Intrinsic {
2313             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2314             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2315             definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2316         },
2317         "ld3_dup_u8" => Intrinsic {
2318             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2319             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2320             definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2321         },
2322         "ld3_dup_s16" => Intrinsic {
2323             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2324             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2325             definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2326         },
2327         "ld3_dup_u16" => Intrinsic {
2328             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2329             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2330             definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2331         },
2332         "ld3_dup_s32" => Intrinsic {
2333             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2334             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2335             definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2336         },
2337         "ld3_dup_u32" => Intrinsic {
2338             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2339             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2340             definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2341         },
2342         "ld3_dup_s64" => Intrinsic {
2343             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2344             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2345             definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2346         },
2347         "ld3_dup_u64" => Intrinsic {
2348             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2349             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2350             definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2351         },
2352         "ld3_dup_f32" => Intrinsic {
2353             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2354             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2355             definition: Named("llvm.aarch64.neon.ld3.v2f32.p0f32")
2356         },
2357         "ld3_dup_f64" => Intrinsic {
2358             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2359             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2360             definition: Named("llvm.aarch64.neon.ld3.v1f64.p0f64")
2361         },
2362         "ld3q_dup_s8" => Intrinsic {
2363             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2364             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2365             definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2366         },
2367         "ld3q_dup_u8" => Intrinsic {
2368             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2369             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2370             definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2371         },
2372         "ld3q_dup_s16" => Intrinsic {
2373             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2374             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2375             definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2376         },
2377         "ld3q_dup_u16" => Intrinsic {
2378             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2379             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2380             definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2381         },
2382         "ld3q_dup_s32" => Intrinsic {
2383             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2384             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2385             definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2386         },
2387         "ld3q_dup_u32" => Intrinsic {
2388             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2389             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2390             definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2391         },
2392         "ld3q_dup_s64" => Intrinsic {
2393             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2394             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2395             definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2396         },
2397         "ld3q_dup_u64" => Intrinsic {
2398             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2399             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2400             definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2401         },
2402         "ld3q_dup_f32" => Intrinsic {
2403             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2404             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2405             definition: Named("llvm.aarch64.neon.ld3.v4f32.p0f32")
2406         },
2407         "ld3q_dup_f64" => Intrinsic {
2408             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2409             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2410             definition: Named("llvm.aarch64.neon.ld3.v2f64.p0f64")
2411         },
2412         "ld4_dup_s8" => Intrinsic {
2413             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2414             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG },
2415             definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2416         },
2417         "ld4_dup_u8" => Intrinsic {
2418             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2419             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG },
2420             definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2421         },
2422         "ld4_dup_s16" => Intrinsic {
2423             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2424             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG },
2425             definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2426         },
2427         "ld4_dup_u16" => Intrinsic {
2428             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2429             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG },
2430             definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2431         },
2432         "ld4_dup_s32" => Intrinsic {
2433             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2434             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG },
2435             definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2436         },
2437         "ld4_dup_u32" => Intrinsic {
2438             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2439             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG },
2440             definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2441         },
2442         "ld4_dup_s64" => Intrinsic {
2443             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2444             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG },
2445             definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2446         },
2447         "ld4_dup_u64" => Intrinsic {
2448             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2449             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG },
2450             definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2451         },
2452         "ld4_dup_f32" => Intrinsic {
2453             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2454             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG },
2455             definition: Named("llvm.aarch64.neon.ld4.v2f32.p0f32")
2456         },
2457         "ld4_dup_f64" => Intrinsic {
2458             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2459             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG },
2460             definition: Named("llvm.aarch64.neon.ld4.v1f64.p0f64")
2461         },
2462         "ld4q_dup_s8" => Intrinsic {
2463             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS },
2464             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG },
2465             definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2466         },
2467         "ld4q_dup_u8" => Intrinsic {
2468             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS },
2469             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG },
2470             definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2471         },
2472         "ld4q_dup_s16" => Intrinsic {
2473             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS },
2474             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG },
2475             definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2476         },
2477         "ld4q_dup_u16" => Intrinsic {
2478             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS },
2479             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG },
2480             definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2481         },
2482         "ld4q_dup_s32" => Intrinsic {
2483             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS },
2484             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG },
2485             definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2486         },
2487         "ld4q_dup_u32" => Intrinsic {
2488             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS },
2489             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG },
2490             definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2491         },
2492         "ld4q_dup_s64" => Intrinsic {
2493             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS },
2494             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG },
2495             definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2496         },
2497         "ld4q_dup_u64" => Intrinsic {
2498             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS },
2499             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG },
2500             definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2501         },
2502         "ld4q_dup_f32" => Intrinsic {
2503             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS },
2504             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG },
2505             definition: Named("llvm.aarch64.neon.ld4.v4f32.p0f32")
2506         },
2507         "ld4q_dup_f64" => Intrinsic {
2508             inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS },
2509             output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG },
2510             definition: Named("llvm.aarch64.neon.ld4.v2f64.p0f64")
2511         },
2512         "padd_s8" => Intrinsic {
2513             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2514             output: &::I8x8,
2515             definition: Named("llvm.aarch64.neon.addp.v8i8")
2516         },
2517         "padd_u8" => Intrinsic {
2518             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2519             output: &::U8x8,
2520             definition: Named("llvm.aarch64.neon.addp.v8i8")
2521         },
2522         "padd_s16" => Intrinsic {
2523             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2524             output: &::I16x4,
2525             definition: Named("llvm.aarch64.neon.addp.v4i16")
2526         },
2527         "padd_u16" => Intrinsic {
2528             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2529             output: &::U16x4,
2530             definition: Named("llvm.aarch64.neon.addp.v4i16")
2531         },
2532         "padd_s32" => Intrinsic {
2533             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2534             output: &::I32x2,
2535             definition: Named("llvm.aarch64.neon.addp.v2i32")
2536         },
2537         "padd_u32" => Intrinsic {
2538             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2539             output: &::U32x2,
2540             definition: Named("llvm.aarch64.neon.addp.v2i32")
2541         },
2542         "padd_f32" => Intrinsic {
2543             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2544             output: &::F32x2,
2545             definition: Named("llvm.aarch64.neon.addp.v2f32")
2546         },
2547         "paddq_s8" => Intrinsic {
2548             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2549             output: &::I8x16,
2550             definition: Named("llvm.aarch64.neon.addp.v16i8")
2551         },
2552         "paddq_u8" => Intrinsic {
2553             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2554             output: &::U8x16,
2555             definition: Named("llvm.aarch64.neon.addp.v16i8")
2556         },
2557         "paddq_s16" => Intrinsic {
2558             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2559             output: &::I16x8,
2560             definition: Named("llvm.aarch64.neon.addp.v8i16")
2561         },
2562         "paddq_u16" => Intrinsic {
2563             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2564             output: &::U16x8,
2565             definition: Named("llvm.aarch64.neon.addp.v8i16")
2566         },
2567         "paddq_s32" => Intrinsic {
2568             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2569             output: &::I32x4,
2570             definition: Named("llvm.aarch64.neon.addp.v4i32")
2571         },
2572         "paddq_u32" => Intrinsic {
2573             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2574             output: &::U32x4,
2575             definition: Named("llvm.aarch64.neon.addp.v4i32")
2576         },
2577         "paddq_f32" => Intrinsic {
2578             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2579             output: &::F32x4,
2580             definition: Named("llvm.aarch64.neon.addp.v4f32")
2581         },
2582         "paddq_s64" => Intrinsic {
2583             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2584             output: &::I64x2,
2585             definition: Named("llvm.aarch64.neon.addp.v2i64")
2586         },
2587         "paddq_u64" => Intrinsic {
2588             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2589             output: &::U64x2,
2590             definition: Named("llvm.aarch64.neon.addp.v2i64")
2591         },
2592         "paddq_f64" => Intrinsic {
2593             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2594             output: &::F64x2,
2595             definition: Named("llvm.aarch64.neon.addp.v2f64")
2596         },
2597         "paddl_s16" => Intrinsic {
2598             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
2599             output: &::I16x4,
2600             definition: Named("llvm.aarch64.neon.saddlp.v4i16.v8i8")
2601         },
2602         "paddl_u16" => Intrinsic {
2603             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
2604             output: &::U16x4,
2605             definition: Named("llvm.aarch64.neon.uaddlp.v4i16.v8i8")
2606         },
2607         "paddl_s32" => Intrinsic {
2608             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
2609             output: &::I32x2,
2610             definition: Named("llvm.aarch64.neon.saddlp.v2i32.v4i16")
2611         },
2612         "paddl_u32" => Intrinsic {
2613             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
2614             output: &::U32x2,
2615             definition: Named("llvm.aarch64.neon.uaddlp.v2i32.v4i16")
2616         },
2617         "paddl_s64" => Intrinsic {
2618             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
2619             output: &::I64x1,
2620             definition: Named("llvm.aarch64.neon.saddlp.v1i64.v2i32")
2621         },
2622         "paddl_u64" => Intrinsic {
2623             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
2624             output: &::U64x1,
2625             definition: Named("llvm.aarch64.neon.uaddlp.v1i64.v2i32")
2626         },
2627         "paddlq_s16" => Intrinsic {
2628             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
2629             output: &::I16x8,
2630             definition: Named("llvm.aarch64.neon.saddlp.v8i16.v16i8")
2631         },
2632         "paddlq_u16" => Intrinsic {
2633             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
2634             output: &::U16x8,
2635             definition: Named("llvm.aarch64.neon.uaddlp.v8i16.v16i8")
2636         },
2637         "paddlq_s32" => Intrinsic {
2638             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
2639             output: &::I32x4,
2640             definition: Named("llvm.aarch64.neon.saddlp.v4i32.v8i16")
2641         },
2642         "paddlq_u32" => Intrinsic {
2643             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
2644             output: &::U32x4,
2645             definition: Named("llvm.aarch64.neon.uaddlp.v4i32.v8i16")
2646         },
2647         "paddlq_s64" => Intrinsic {
2648             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
2649             output: &::I64x2,
2650             definition: Named("llvm.aarch64.neon.saddlp.v2i64.v4i32")
2651         },
2652         "paddlq_u64" => Intrinsic {
2653             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
2654             output: &::U64x2,
2655             definition: Named("llvm.aarch64.neon.uaddlp.v2i64.v4i32")
2656         },
2657         "pmax_s8" => Intrinsic {
2658             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2659             output: &::I8x8,
2660             definition: Named("llvm.aarch64.neon.smaxp.v8i8")
2661         },
2662         "pmax_u8" => Intrinsic {
2663             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2664             output: &::U8x8,
2665             definition: Named("llvm.aarch64.neon.umaxp.v8i8")
2666         },
2667         "pmax_s16" => Intrinsic {
2668             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2669             output: &::I16x4,
2670             definition: Named("llvm.aarch64.neon.smaxp.v4i16")
2671         },
2672         "pmax_u16" => Intrinsic {
2673             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2674             output: &::U16x4,
2675             definition: Named("llvm.aarch64.neon.umaxp.v4i16")
2676         },
2677         "pmax_s32" => Intrinsic {
2678             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2679             output: &::I32x2,
2680             definition: Named("llvm.aarch64.neon.smaxp.v2i32")
2681         },
2682         "pmax_u32" => Intrinsic {
2683             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2684             output: &::U32x2,
2685             definition: Named("llvm.aarch64.neon.umaxp.v2i32")
2686         },
2687         "pmax_f32" => Intrinsic {
2688             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2689             output: &::F32x2,
2690             definition: Named("llvm.aarch64.neon.fmaxp.v2f32")
2691         },
2692         "pmaxq_s8" => Intrinsic {
2693             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2694             output: &::I8x16,
2695             definition: Named("llvm.aarch64.neon.smaxp.v16i8")
2696         },
2697         "pmaxq_u8" => Intrinsic {
2698             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2699             output: &::U8x16,
2700             definition: Named("llvm.aarch64.neon.umaxp.v16i8")
2701         },
2702         "pmaxq_s16" => Intrinsic {
2703             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2704             output: &::I16x8,
2705             definition: Named("llvm.aarch64.neon.smaxp.v8i16")
2706         },
2707         "pmaxq_u16" => Intrinsic {
2708             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2709             output: &::U16x8,
2710             definition: Named("llvm.aarch64.neon.umaxp.v8i16")
2711         },
2712         "pmaxq_s32" => Intrinsic {
2713             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2714             output: &::I32x4,
2715             definition: Named("llvm.aarch64.neon.smaxp.v4i32")
2716         },
2717         "pmaxq_u32" => Intrinsic {
2718             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2719             output: &::U32x4,
2720             definition: Named("llvm.aarch64.neon.umaxp.v4i32")
2721         },
2722         "pmaxq_f32" => Intrinsic {
2723             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2724             output: &::F32x4,
2725             definition: Named("llvm.aarch64.neon.fmaxp.v4f32")
2726         },
2727         "pmaxq_s64" => Intrinsic {
2728             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2729             output: &::I64x2,
2730             definition: Named("llvm.aarch64.neon.smaxp.v2i64")
2731         },
2732         "pmaxq_u64" => Intrinsic {
2733             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2734             output: &::U64x2,
2735             definition: Named("llvm.aarch64.neon.umaxp.v2i64")
2736         },
2737         "pmaxq_f64" => Intrinsic {
2738             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2739             output: &::F64x2,
2740             definition: Named("llvm.aarch64.neon.fmaxp.v2f64")
2741         },
2742         "pmin_s8" => Intrinsic {
2743             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2744             output: &::I8x8,
2745             definition: Named("llvm.aarch64.neon.sminp.v8i8")
2746         },
2747         "pmin_u8" => Intrinsic {
2748             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2749             output: &::U8x8,
2750             definition: Named("llvm.aarch64.neon.uminp.v8i8")
2751         },
2752         "pmin_s16" => Intrinsic {
2753             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2754             output: &::I16x4,
2755             definition: Named("llvm.aarch64.neon.sminp.v4i16")
2756         },
2757         "pmin_u16" => Intrinsic {
2758             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2759             output: &::U16x4,
2760             definition: Named("llvm.aarch64.neon.uminp.v4i16")
2761         },
2762         "pmin_s32" => Intrinsic {
2763             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2764             output: &::I32x2,
2765             definition: Named("llvm.aarch64.neon.sminp.v2i32")
2766         },
2767         "pmin_u32" => Intrinsic {
2768             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2769             output: &::U32x2,
2770             definition: Named("llvm.aarch64.neon.uminp.v2i32")
2771         },
2772         "pmin_f32" => Intrinsic {
2773             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2774             output: &::F32x2,
2775             definition: Named("llvm.aarch64.neon.fminp.v2f32")
2776         },
2777         "pminq_s8" => Intrinsic {
2778             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2779             output: &::I8x16,
2780             definition: Named("llvm.aarch64.neon.sminp.v16i8")
2781         },
2782         "pminq_u8" => Intrinsic {
2783             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2784             output: &::U8x16,
2785             definition: Named("llvm.aarch64.neon.uminp.v16i8")
2786         },
2787         "pminq_s16" => Intrinsic {
2788             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2789             output: &::I16x8,
2790             definition: Named("llvm.aarch64.neon.sminp.v8i16")
2791         },
2792         "pminq_u16" => Intrinsic {
2793             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2794             output: &::U16x8,
2795             definition: Named("llvm.aarch64.neon.uminp.v8i16")
2796         },
2797         "pminq_s32" => Intrinsic {
2798             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2799             output: &::I32x4,
2800             definition: Named("llvm.aarch64.neon.sminp.v4i32")
2801         },
2802         "pminq_u32" => Intrinsic {
2803             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2804             output: &::U32x4,
2805             definition: Named("llvm.aarch64.neon.uminp.v4i32")
2806         },
2807         "pminq_f32" => Intrinsic {
2808             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2809             output: &::F32x4,
2810             definition: Named("llvm.aarch64.neon.fminp.v4f32")
2811         },
2812         "pminq_s64" => Intrinsic {
2813             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2814             output: &::I64x2,
2815             definition: Named("llvm.aarch64.neon.sminp.v2i64")
2816         },
2817         "pminq_u64" => Intrinsic {
2818             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2819             output: &::U64x2,
2820             definition: Named("llvm.aarch64.neon.uminp.v2i64")
2821         },
2822         "pminq_f64" => Intrinsic {
2823             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2824             output: &::F64x2,
2825             definition: Named("llvm.aarch64.neon.fminp.v2f64")
2826         },
2827         "pmaxnm_s8" => Intrinsic {
2828             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
2829             output: &::I8x8,
2830             definition: Named("llvm.aarch64.neon.smaxnmp.v8i8")
2831         },
2832         "pmaxnm_u8" => Intrinsic {
2833             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2834             output: &::U8x8,
2835             definition: Named("llvm.aarch64.neon.umaxnmp.v8i8")
2836         },
2837         "pmaxnm_s16" => Intrinsic {
2838             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
2839             output: &::I16x4,
2840             definition: Named("llvm.aarch64.neon.smaxnmp.v4i16")
2841         },
2842         "pmaxnm_u16" => Intrinsic {
2843             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
2844             output: &::U16x4,
2845             definition: Named("llvm.aarch64.neon.umaxnmp.v4i16")
2846         },
2847         "pmaxnm_s32" => Intrinsic {
2848             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
2849             output: &::I32x2,
2850             definition: Named("llvm.aarch64.neon.smaxnmp.v2i32")
2851         },
2852         "pmaxnm_u32" => Intrinsic {
2853             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
2854             output: &::U32x2,
2855             definition: Named("llvm.aarch64.neon.umaxnmp.v2i32")
2856         },
2857         "pmaxnm_f32" => Intrinsic {
2858             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2859             output: &::F32x2,
2860             definition: Named("llvm.aarch64.neon.fmaxnmp.v2f32")
2861         },
2862         "pmaxnmq_s8" => Intrinsic {
2863             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
2864             output: &::I8x16,
2865             definition: Named("llvm.aarch64.neon.smaxnmp.v16i8")
2866         },
2867         "pmaxnmq_u8" => Intrinsic {
2868             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
2869             output: &::U8x16,
2870             definition: Named("llvm.aarch64.neon.umaxnmp.v16i8")
2871         },
2872         "pmaxnmq_s16" => Intrinsic {
2873             inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
2874             output: &::I16x8,
2875             definition: Named("llvm.aarch64.neon.smaxnmp.v8i16")
2876         },
2877         "pmaxnmq_u16" => Intrinsic {
2878             inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
2879             output: &::U16x8,
2880             definition: Named("llvm.aarch64.neon.umaxnmp.v8i16")
2881         },
2882         "pmaxnmq_s32" => Intrinsic {
2883             inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
2884             output: &::I32x4,
2885             definition: Named("llvm.aarch64.neon.smaxnmp.v4i32")
2886         },
2887         "pmaxnmq_u32" => Intrinsic {
2888             inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
2889             output: &::U32x4,
2890             definition: Named("llvm.aarch64.neon.umaxnmp.v4i32")
2891         },
2892         "pmaxnmq_f32" => Intrinsic {
2893             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2894             output: &::F32x4,
2895             definition: Named("llvm.aarch64.neon.fmaxnmp.v4f32")
2896         },
2897         "pmaxnmq_s64" => Intrinsic {
2898             inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
2899             output: &::I64x2,
2900             definition: Named("llvm.aarch64.neon.smaxnmp.v2i64")
2901         },
2902         "pmaxnmq_u64" => Intrinsic {
2903             inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
2904             output: &::U64x2,
2905             definition: Named("llvm.aarch64.neon.umaxnmp.v2i64")
2906         },
2907         "pmaxnmq_f64" => Intrinsic {
2908             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2909             output: &::F64x2,
2910             definition: Named("llvm.aarch64.neon.fmaxnmp.v2f64")
2911         },
2912         "pminnm_f32" => Intrinsic {
2913             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
2914             output: &::F32x2,
2915             definition: Named("llvm.aarch64.neon.fminnmp.v2f32")
2916         },
2917         "pminnmq_f32" => Intrinsic {
2918             inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2919             output: &::F32x4,
2920             definition: Named("llvm.aarch64.neon.fminnmp.v4f32")
2921         },
2922         "pminnmq_f64" => Intrinsic {
2923             inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS },
2924             output: &::F64x2,
2925             definition: Named("llvm.aarch64.neon.fminnmp.v2f64")
2926         },
2927         "addv_s8" => Intrinsic {
2928             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
2929             output: &::I8,
2930             definition: Named("llvm.aarch64.neon.saddv.i8.v8i8")
2931         },
2932         "addv_u8" => Intrinsic {
2933             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
2934             output: &::U8,
2935             definition: Named("llvm.aarch64.neon.uaddv.i8.v8i8")
2936         },
2937         "addv_s16" => Intrinsic {
2938             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
2939             output: &::I16,
2940             definition: Named("llvm.aarch64.neon.saddv.i16.v4i16")
2941         },
2942         "addv_u16" => Intrinsic {
2943             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
2944             output: &::U16,
2945             definition: Named("llvm.aarch64.neon.uaddv.i16.v4i16")
2946         },
2947         "addv_s32" => Intrinsic {
2948             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
2949             output: &::I32,
2950             definition: Named("llvm.aarch64.neon.saddv.i32.v2i32")
2951         },
2952         "addv_u32" => Intrinsic {
2953             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
2954             output: &::U32,
2955             definition: Named("llvm.aarch64.neon.uaddv.i32.v2i32")
2956         },
2957         "addv_f32" => Intrinsic {
2958             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
2959             output: &::F32,
2960             definition: Named("llvm.aarch64.neon.faddv.f32.v2f32")
2961         },
2962         "addvq_s8" => Intrinsic {
2963             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
2964             output: &::I8,
2965             definition: Named("llvm.aarch64.neon.saddv.i8.v16i8")
2966         },
2967         "addvq_u8" => Intrinsic {
2968             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
2969             output: &::U8,
2970             definition: Named("llvm.aarch64.neon.uaddv.i8.v16i8")
2971         },
2972         "addvq_s16" => Intrinsic {
2973             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
2974             output: &::I16,
2975             definition: Named("llvm.aarch64.neon.saddv.i16.v8i16")
2976         },
2977         "addvq_u16" => Intrinsic {
2978             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
2979             output: &::U16,
2980             definition: Named("llvm.aarch64.neon.uaddv.i16.v8i16")
2981         },
2982         "addvq_s32" => Intrinsic {
2983             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
2984             output: &::I32,
2985             definition: Named("llvm.aarch64.neon.saddv.i32.v4i32")
2986         },
2987         "addvq_u32" => Intrinsic {
2988             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
2989             output: &::U32,
2990             definition: Named("llvm.aarch64.neon.uaddv.i32.v4i32")
2991         },
2992         "addvq_f32" => Intrinsic {
2993             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
2994             output: &::F32,
2995             definition: Named("llvm.aarch64.neon.faddv.f32.v4f32")
2996         },
2997         "addvq_s64" => Intrinsic {
2998             inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
2999             output: &::I64,
3000             definition: Named("llvm.aarch64.neon.saddv.i64.v2i64")
3001         },
3002         "addvq_u64" => Intrinsic {
3003             inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
3004             output: &::U64,
3005             definition: Named("llvm.aarch64.neon.uaddv.i64.v2i64")
3006         },
3007         "addvq_f64" => Intrinsic {
3008             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3009             output: &::F64,
3010             definition: Named("llvm.aarch64.neon.faddv.f64.v2f64")
3011         },
3012         "addlv_s8" => Intrinsic {
3013             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3014             output: &::I16,
3015             definition: Named("llvm.aarch64.neon.saddlv.i16.v8i8")
3016         },
3017         "addlv_u8" => Intrinsic {
3018             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3019             output: &::U16,
3020             definition: Named("llvm.aarch64.neon.uaddlv.i16.v8i8")
3021         },
3022         "addlv_s16" => Intrinsic {
3023             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3024             output: &::I32,
3025             definition: Named("llvm.aarch64.neon.saddlv.i32.v4i16")
3026         },
3027         "addlv_u16" => Intrinsic {
3028             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3029             output: &::U32,
3030             definition: Named("llvm.aarch64.neon.uaddlv.i32.v4i16")
3031         },
3032         "addlv_s32" => Intrinsic {
3033             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3034             output: &::I64,
3035             definition: Named("llvm.aarch64.neon.saddlv.i64.v2i32")
3036         },
3037         "addlv_u32" => Intrinsic {
3038             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3039             output: &::U64,
3040             definition: Named("llvm.aarch64.neon.uaddlv.i64.v2i32")
3041         },
3042         "addlvq_s8" => Intrinsic {
3043             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3044             output: &::I16,
3045             definition: Named("llvm.aarch64.neon.saddlv.i16.v16i8")
3046         },
3047         "addlvq_u8" => Intrinsic {
3048             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3049             output: &::U16,
3050             definition: Named("llvm.aarch64.neon.uaddlv.i16.v16i8")
3051         },
3052         "addlvq_s16" => Intrinsic {
3053             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3054             output: &::I32,
3055             definition: Named("llvm.aarch64.neon.saddlv.i32.v8i16")
3056         },
3057         "addlvq_u16" => Intrinsic {
3058             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3059             output: &::U32,
3060             definition: Named("llvm.aarch64.neon.uaddlv.i32.v8i16")
3061         },
3062         "addlvq_s32" => Intrinsic {
3063             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3064             output: &::I64,
3065             definition: Named("llvm.aarch64.neon.saddlv.i64.v4i32")
3066         },
3067         "addlvq_u32" => Intrinsic {
3068             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3069             output: &::U64,
3070             definition: Named("llvm.aarch64.neon.uaddlv.i64.v4i32")
3071         },
3072         "maxv_s8" => Intrinsic {
3073             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3074             output: &::I8,
3075             definition: Named("llvm.aarch64.neon.smaxv.i8.v8i8")
3076         },
3077         "maxv_u8" => Intrinsic {
3078             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3079             output: &::U8,
3080             definition: Named("llvm.aarch64.neon.umaxv.i8.v8i8")
3081         },
3082         "maxv_s16" => Intrinsic {
3083             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3084             output: &::I16,
3085             definition: Named("llvm.aarch64.neon.smaxv.i16.v4i16")
3086         },
3087         "maxv_u16" => Intrinsic {
3088             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3089             output: &::U16,
3090             definition: Named("llvm.aarch64.neon.umaxv.i16.v4i16")
3091         },
3092         "maxv_s32" => Intrinsic {
3093             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3094             output: &::I32,
3095             definition: Named("llvm.aarch64.neon.smaxv.i32.v2i32")
3096         },
3097         "maxv_u32" => Intrinsic {
3098             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3099             output: &::U32,
3100             definition: Named("llvm.aarch64.neon.umaxv.i32.v2i32")
3101         },
3102         "maxv_f32" => Intrinsic {
3103             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3104             output: &::F32,
3105             definition: Named("llvm.aarch64.neon.fmaxv.f32.v2f32")
3106         },
3107         "maxvq_s8" => Intrinsic {
3108             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3109             output: &::I8,
3110             definition: Named("llvm.aarch64.neon.smaxv.i8.v16i8")
3111         },
3112         "maxvq_u8" => Intrinsic {
3113             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3114             output: &::U8,
3115             definition: Named("llvm.aarch64.neon.umaxv.i8.v16i8")
3116         },
3117         "maxvq_s16" => Intrinsic {
3118             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3119             output: &::I16,
3120             definition: Named("llvm.aarch64.neon.smaxv.i16.v8i16")
3121         },
3122         "maxvq_u16" => Intrinsic {
3123             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3124             output: &::U16,
3125             definition: Named("llvm.aarch64.neon.umaxv.i16.v8i16")
3126         },
3127         "maxvq_s32" => Intrinsic {
3128             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3129             output: &::I32,
3130             definition: Named("llvm.aarch64.neon.smaxv.i32.v4i32")
3131         },
3132         "maxvq_u32" => Intrinsic {
3133             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3134             output: &::U32,
3135             definition: Named("llvm.aarch64.neon.umaxv.i32.v4i32")
3136         },
3137         "maxvq_f32" => Intrinsic {
3138             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3139             output: &::F32,
3140             definition: Named("llvm.aarch64.neon.fmaxv.f32.v4f32")
3141         },
3142         "maxvq_f64" => Intrinsic {
3143             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3144             output: &::F64,
3145             definition: Named("llvm.aarch64.neon.fmaxv.f64.v2f64")
3146         },
3147         "minv_s8" => Intrinsic {
3148             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
3149             output: &::I8,
3150             definition: Named("llvm.aarch64.neon.sminv.i8.v8i8")
3151         },
3152         "minv_u8" => Intrinsic {
3153             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
3154             output: &::U8,
3155             definition: Named("llvm.aarch64.neon.uminv.i8.v8i8")
3156         },
3157         "minv_s16" => Intrinsic {
3158             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
3159             output: &::I16,
3160             definition: Named("llvm.aarch64.neon.sminv.i16.v4i16")
3161         },
3162         "minv_u16" => Intrinsic {
3163             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
3164             output: &::U16,
3165             definition: Named("llvm.aarch64.neon.uminv.i16.v4i16")
3166         },
3167         "minv_s32" => Intrinsic {
3168             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
3169             output: &::I32,
3170             definition: Named("llvm.aarch64.neon.sminv.i32.v2i32")
3171         },
3172         "minv_u32" => Intrinsic {
3173             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
3174             output: &::U32,
3175             definition: Named("llvm.aarch64.neon.uminv.i32.v2i32")
3176         },
3177         "minv_f32" => Intrinsic {
3178             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3179             output: &::F32,
3180             definition: Named("llvm.aarch64.neon.fminv.f32.v2f32")
3181         },
3182         "minvq_s8" => Intrinsic {
3183             inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
3184             output: &::I8,
3185             definition: Named("llvm.aarch64.neon.sminv.i8.v16i8")
3186         },
3187         "minvq_u8" => Intrinsic {
3188             inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
3189             output: &::U8,
3190             definition: Named("llvm.aarch64.neon.uminv.i8.v16i8")
3191         },
3192         "minvq_s16" => Intrinsic {
3193             inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
3194             output: &::I16,
3195             definition: Named("llvm.aarch64.neon.sminv.i16.v8i16")
3196         },
3197         "minvq_u16" => Intrinsic {
3198             inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
3199             output: &::U16,
3200             definition: Named("llvm.aarch64.neon.uminv.i16.v8i16")
3201         },
3202         "minvq_s32" => Intrinsic {
3203             inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
3204             output: &::I32,
3205             definition: Named("llvm.aarch64.neon.sminv.i32.v4i32")
3206         },
3207         "minvq_u32" => Intrinsic {
3208             inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
3209             output: &::U32,
3210             definition: Named("llvm.aarch64.neon.uminv.i32.v4i32")
3211         },
3212         "minvq_f32" => Intrinsic {
3213             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3214             output: &::F32,
3215             definition: Named("llvm.aarch64.neon.fminv.f32.v4f32")
3216         },
3217         "minvq_f64" => Intrinsic {
3218             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3219             output: &::F64,
3220             definition: Named("llvm.aarch64.neon.fminv.f64.v2f64")
3221         },
3222         "maxnmv_f32" => Intrinsic {
3223             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3224             output: &::F32,
3225             definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v2f32")
3226         },
3227         "maxnmvq_f32" => Intrinsic {
3228             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3229             output: &::F32,
3230             definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v4f32")
3231         },
3232         "maxnmvq_f64" => Intrinsic {
3233             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3234             output: &::F64,
3235             definition: Named("llvm.aarch64.neon.fmaxnmv.f64.v2f64")
3236         },
3237         "minnmv_f32" => Intrinsic {
3238             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
3239             output: &::F32,
3240             definition: Named("llvm.aarch64.neon.fminnmv.f32.v2f32")
3241         },
3242         "minnmvq_f32" => Intrinsic {
3243             inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
3244             output: &::F32,
3245             definition: Named("llvm.aarch64.neon.fminnmv.f32.v4f32")
3246         },
3247         "minnmvq_f64" => Intrinsic {
3248             inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS },
3249             output: &::F64,
3250             definition: Named("llvm.aarch64.neon.fminnmv.f64.v2f64")
3251         },
3252         "qtbl1_s8" => Intrinsic {
3253             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x8]; &INPUTS },
3254             output: &::I8x8,
3255             definition: Named("llvm.aarch64.neon.tbl1.v8i8")
3256         },
3257         "qtbl1_u8" => Intrinsic {
3258             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x8]; &INPUTS },
3259             output: &::U8x8,
3260             definition: Named("llvm.aarch64.neon.tbl1.v8i8")
3261         },
3262         "qtbl1q_s8" => Intrinsic {
3263             inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS },
3264             output: &::I8x16,
3265             definition: Named("llvm.aarch64.neon.tbl1.v16i8")
3266         },
3267         "qtbl1q_u8" => Intrinsic {
3268             inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
3269             output: &::U8x16,
3270             definition: Named("llvm.aarch64.neon.tbl1.v16i8")
3271         },
3272         "qtbx1_s8" => Intrinsic {
3273             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x16, &::U8x8]; &INPUTS },
3274             output: &::I8x8,
3275             definition: Named("llvm.aarch64.neon.tbx1.v8i8")
3276         },
3277         "qtbx1_u8" => Intrinsic {
3278             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x16, &::U8x8]; &INPUTS },
3279             output: &::U8x8,
3280             definition: Named("llvm.aarch64.neon.tbx1.v8i8")
3281         },
3282         "qtbx1q_s8" => Intrinsic {
3283             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::U8x16]; &INPUTS },
3284             output: &::I8x16,
3285             definition: Named("llvm.aarch64.neon.tbx1.v16i8")
3286         },
3287         "qtbx1q_u8" => Intrinsic {
3288             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &INPUTS },
3289             output: &::U8x16,
3290             definition: Named("llvm.aarch64.neon.tbx1.v16i8")
3291         },
3292         "qtbl2_s8" => Intrinsic {
3293             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3294             output: &::I8x8,
3295             definition: Named("llvm.aarch64.neon.tbl2.v8i8")
3296         },
3297         "qtbl2_u8" => Intrinsic {
3298             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3299             output: &::U8x8,
3300             definition: Named("llvm.aarch64.neon.tbl2.v8i8")
3301         },
3302         "qtbl2q_s8" => Intrinsic {
3303             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3304             output: &::I8x16,
3305             definition: Named("llvm.aarch64.neon.tbl2.v16i8")
3306         },
3307         "qtbl2q_u8" => Intrinsic {
3308             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3309             output: &::U8x16,
3310             definition: Named("llvm.aarch64.neon.tbl2.v16i8")
3311         },
3312         "qtbx2_s8" => Intrinsic {
3313             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3314             output: &::I8x8,
3315             definition: Named("llvm.aarch64.neon.tbx2.v8i8")
3316         },
3317         "qtbx2_u8" => Intrinsic {
3318             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3319             output: &::U8x8,
3320             definition: Named("llvm.aarch64.neon.tbx2.v8i8")
3321         },
3322         "qtbx2q_s8" => Intrinsic {
3323             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3324             output: &::I8x16,
3325             definition: Named("llvm.aarch64.neon.tbx2.v16i8")
3326         },
3327         "qtbx2q_u8" => Intrinsic {
3328             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3329             output: &::U8x16,
3330             definition: Named("llvm.aarch64.neon.tbx2.v16i8")
3331         },
3332         "qtbl3_s8" => Intrinsic {
3333             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3334             output: &::I8x8,
3335             definition: Named("llvm.aarch64.neon.tbl3.v8i8")
3336         },
3337         "qtbl3_u8" => Intrinsic {
3338             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3339             output: &::U8x8,
3340             definition: Named("llvm.aarch64.neon.tbl3.v8i8")
3341         },
3342         "qtbl3q_s8" => Intrinsic {
3343             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3344             output: &::I8x16,
3345             definition: Named("llvm.aarch64.neon.tbl3.v16i8")
3346         },
3347         "qtbl3q_u8" => Intrinsic {
3348             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3349             output: &::U8x16,
3350             definition: Named("llvm.aarch64.neon.tbl3.v16i8")
3351         },
3352         "qtbx3_s8" => Intrinsic {
3353             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3354             output: &::I8x8,
3355             definition: Named("llvm.aarch64.neon.tbx3.v8i8")
3356         },
3357         "qtbx3_u8" => Intrinsic {
3358             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3359             output: &::U8x8,
3360             definition: Named("llvm.aarch64.neon.tbx3.v8i8")
3361         },
3362         "qtbx3q_s8" => Intrinsic {
3363             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3364             output: &::I8x16,
3365             definition: Named("llvm.aarch64.neon.tbx3.v16i8")
3366         },
3367         "qtbx3q_u8" => Intrinsic {
3368             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3369             output: &::U8x16,
3370             definition: Named("llvm.aarch64.neon.tbx3.v16i8")
3371         },
3372         "qtbl4_s8" => Intrinsic {
3373             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3374             output: &::I8x8,
3375             definition: Named("llvm.aarch64.neon.tbl4.v8i8")
3376         },
3377         "qtbl4_u8" => Intrinsic {
3378             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3379             output: &::U8x8,
3380             definition: Named("llvm.aarch64.neon.tbl4.v8i8")
3381         },
3382         "qtbl4q_s8" => Intrinsic {
3383             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3384             output: &::I8x16,
3385             definition: Named("llvm.aarch64.neon.tbl4.v16i8")
3386         },
3387         "qtbl4q_u8" => Intrinsic {
3388             inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3389             output: &::U8x16,
3390             definition: Named("llvm.aarch64.neon.tbl4.v16i8")
3391         },
3392         "qtbx4_s8" => Intrinsic {
3393             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3394             output: &::I8x8,
3395             definition: Named("llvm.aarch64.neon.tbx4.v8i8")
3396         },
3397         "qtbx4_u8" => Intrinsic {
3398             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
3399             output: &::U8x8,
3400             definition: Named("llvm.aarch64.neon.tbx4.v8i8")
3401         },
3402         "qtbx4q_s8" => Intrinsic {
3403             inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3404             output: &::I8x16,
3405             definition: Named("llvm.aarch64.neon.tbx4.v16i8")
3406         },
3407         "qtbx4q_u8" => Intrinsic {
3408             inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS },
3409             output: &::U8x16,
3410             definition: Named("llvm.aarch64.neon.tbx4.v16i8")
3411         },
3412         _ => return None,
3413     })
3414 }