1 use crate::builder::Builder;
2 use crate::context::CodegenCx;
4 use crate::type_::Type;
5 use crate::type_of::LayoutLlvmExt;
6 use crate::value::Value;
8 use rustc_ast::ast::LlvmAsmDialect;
9 use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
10 use rustc_codegen_ssa::mir::operand::OperandValue;
11 use rustc_codegen_ssa::mir::place::PlaceRef;
12 use rustc_codegen_ssa::traits::*;
13 use rustc_data_structures::fx::FxHashMap;
15 use rustc_middle::span_bug;
16 use rustc_middle::ty::layout::TyAndLayout;
17 use rustc_span::{Pos, Span};
18 use rustc_target::abi::*;
19 use rustc_target::asm::*;
21 use libc::{c_char, c_uint};
24 impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
25 fn codegen_llvm_inline_asm(
27 ia: &hir::LlvmInlineAsmInner,
28 outputs: Vec<PlaceRef<'tcx, &'ll Value>>,
29 mut inputs: Vec<&'ll Value>,
32 let mut ext_constraints = vec![];
33 let mut output_types = vec![];
35 // Prepare the output operands
36 let mut indirect_outputs = vec![];
37 for (i, (out, &place)) in ia.outputs.iter().zip(&outputs).enumerate() {
39 let operand = self.load_operand(place);
40 if let OperandValue::Immediate(_) = operand.val {
41 inputs.push(operand.immediate());
43 ext_constraints.push(i.to_string());
46 let operand = self.load_operand(place);
47 if let OperandValue::Immediate(_) = operand.val {
48 indirect_outputs.push(operand.immediate());
51 output_types.push(place.layout.llvm_type(self.cx));
54 if !indirect_outputs.is_empty() {
55 indirect_outputs.extend_from_slice(&inputs);
56 inputs = indirect_outputs;
59 let clobbers = ia.clobbers.iter().map(|s| format!("~{{{}}}", &s));
61 // Default per-arch clobbers
62 // Basically what clang does
63 let arch_clobbers = match &self.sess().target.target.arch[..] {
64 "x86" | "x86_64" => vec!["~{dirflag}", "~{fpsr}", "~{flags}"],
65 "mips" | "mips64" => vec!["~{$1}"],
69 let all_constraints = ia
72 .map(|out| out.constraint.to_string())
73 .chain(ia.inputs.iter().map(|s| s.to_string()))
74 .chain(ext_constraints)
76 .chain(arch_clobbers.iter().map(|s| (*s).to_string()))
77 .collect::<Vec<String>>()
80 debug!("Asm Constraints: {}", &all_constraints);
82 // Depending on how many outputs we have, the return type is different
83 let num_outputs = output_types.len();
84 let output_type = match num_outputs {
85 0 => self.type_void(),
87 _ => self.type_struct(&output_types, false),
90 let asm = ia.asm.as_str();
91 let r = inline_asm_call(
107 // Again, based on how many outputs we have
108 let outputs = ia.outputs.iter().zip(&outputs).filter(|&(ref o, _)| !o.is_indirect);
109 for (i, (_, &place)) in outputs.enumerate() {
110 let v = if num_outputs == 1 { r } else { self.extract_value(r, i as u64) };
111 OperandValue::Immediate(v).store(self, place);
117 fn codegen_inline_asm(
119 template: &[InlineAsmTemplatePiece],
120 operands: &[InlineAsmOperandRef<'tcx, Self>],
121 options: InlineAsmOptions,
124 let asm_arch = self.tcx.sess.asm_arch.unwrap();
126 // Collect the types of output operands
127 let mut constraints = vec![];
128 let mut output_types = vec![];
129 let mut op_idx = FxHashMap::default();
130 for (idx, op) in operands.iter().enumerate() {
132 InlineAsmOperandRef::Out { reg, late, place } => {
133 let ty = if let Some(place) = place {
134 llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout)
136 // If the output is discarded, we don't really care what
137 // type is used. We're just using this to tell LLVM to
138 // reserve the register.
139 dummy_output_type(self.cx, reg.reg_class())
141 output_types.push(ty);
142 op_idx.insert(idx, constraints.len());
143 let prefix = if late { "=" } else { "=&" };
144 constraints.push(format!("{}{}", prefix, reg_to_llvm(reg)));
146 InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => {
147 let ty = if let Some(ref out_place) = out_place {
148 llvm_fixup_output_type(self.cx, reg.reg_class(), &out_place.layout)
150 // LLVM required tied operands to have the same type,
151 // so we just use the type of the input.
152 llvm_fixup_output_type(self.cx, reg.reg_class(), &in_value.layout)
154 output_types.push(ty);
155 op_idx.insert(idx, constraints.len());
156 let prefix = if late { "=" } else { "=&" };
157 constraints.push(format!("{}{}", prefix, reg_to_llvm(reg)));
163 // Collect input operands
164 let mut inputs = vec![];
165 for (idx, op) in operands.iter().enumerate() {
167 InlineAsmOperandRef::In { reg, value } => {
169 llvm_fixup_input(self, value.immediate(), reg.reg_class(), &value.layout);
171 op_idx.insert(idx, constraints.len());
172 constraints.push(reg_to_llvm(reg));
174 InlineAsmOperandRef::InOut { reg, late: _, in_value, out_place: _ } => {
175 let value = llvm_fixup_input(
177 in_value.immediate(),
182 constraints.push(format!("{}", op_idx[&idx]));
184 InlineAsmOperandRef::SymFn { instance } => {
185 inputs.push(self.cx.get_fn(instance));
186 op_idx.insert(idx, constraints.len());
187 constraints.push("s".to_string());
189 InlineAsmOperandRef::SymStatic { def_id } => {
190 inputs.push(self.cx.get_static(def_id));
191 op_idx.insert(idx, constraints.len());
192 constraints.push("s".to_string());
198 // Build the template string
199 let mut template_str = String::new();
200 for piece in template {
202 InlineAsmTemplatePiece::String(ref s) => {
206 template_str.push_str("$$");
208 template_str.push(c);
212 template_str.push_str(s)
215 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
216 match operands[operand_idx] {
217 InlineAsmOperandRef::In { reg, .. }
218 | InlineAsmOperandRef::Out { reg, .. }
219 | InlineAsmOperandRef::InOut { reg, .. } => {
220 let modifier = modifier_to_llvm(asm_arch, reg.reg_class(), modifier);
221 if let Some(modifier) = modifier {
222 template_str.push_str(&format!(
224 op_idx[&operand_idx], modifier
227 template_str.push_str(&format!("${{{}}}", op_idx[&operand_idx]));
230 InlineAsmOperandRef::Const { ref string } => {
231 // Const operands get injected directly into the template
232 template_str.push_str(string);
234 InlineAsmOperandRef::SymFn { .. }
235 | InlineAsmOperandRef::SymStatic { .. } => {
236 // Only emit the raw symbol name
237 template_str.push_str(&format!("${{{}:c}}", op_idx[&operand_idx]));
244 if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
246 InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
247 constraints.push("~{cc}".to_string());
249 InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
250 constraints.extend_from_slice(&[
251 "~{dirflag}".to_string(),
252 "~{fpsr}".to_string(),
253 "~{flags}".to_string(),
256 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
257 InlineAsmArch::Nvptx64 => {}
258 InlineAsmArch::Hexagon => {}
261 if !options.contains(InlineAsmOptions::NOMEM) {
262 // This is actually ignored by LLVM, but it's probably best to keep
263 // it just in case. LLVM instead uses the ReadOnly/ReadNone
264 // attributes on the call instruction to optimize.
265 constraints.push("~{memory}".to_string());
267 let volatile = !options.contains(InlineAsmOptions::PURE);
268 let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
269 let output_type = match &output_types[..] {
270 [] => self.type_void(),
272 tys => self.type_struct(&tys, false),
274 let dialect = match asm_arch {
275 InlineAsmArch::X86 | InlineAsmArch::X86_64
276 if !options.contains(InlineAsmOptions::ATT_SYNTAX) =>
278 LlvmAsmDialect::Intel
280 _ => LlvmAsmDialect::Att,
282 let result = inline_asm_call(
285 &constraints.join(","),
293 .unwrap_or_else(|| span_bug!(line_spans[0], "LLVM asm constraint validation failed"));
295 if options.contains(InlineAsmOptions::PURE) {
296 if options.contains(InlineAsmOptions::NOMEM) {
297 llvm::Attribute::ReadNone.apply_callsite(llvm::AttributePlace::Function, result);
298 } else if options.contains(InlineAsmOptions::READONLY) {
299 llvm::Attribute::ReadOnly.apply_callsite(llvm::AttributePlace::Function, result);
302 if options.contains(InlineAsmOptions::NOMEM) {
303 llvm::Attribute::InaccessibleMemOnly
304 .apply_callsite(llvm::AttributePlace::Function, result);
306 // LLVM doesn't have an attribute to represent ReadOnly + SideEffect
310 // Write results to outputs
311 for (idx, op) in operands.iter().enumerate() {
312 if let InlineAsmOperandRef::Out { reg, place: Some(place), .. }
313 | InlineAsmOperandRef::InOut { reg, out_place: Some(place), .. } = *op
315 let value = if output_types.len() == 1 {
318 self.extract_value(result, op_idx[&idx] as u64)
320 let value = llvm_fixup_output(self, value, reg.reg_class(), &place.layout);
321 OperandValue::Immediate(value).store(self, place);
327 impl AsmMethods for CodegenCx<'ll, 'tcx> {
328 fn codegen_global_asm(&self, ga: &hir::GlobalAsm) {
329 let asm = ga.asm.as_str();
331 llvm::LLVMRustAppendModuleInlineAsm(self.llmod, asm.as_ptr().cast(), asm.len());
337 bx: &mut Builder<'a, 'll, 'tcx>,
340 inputs: &[&'ll Value],
341 output: &'ll llvm::Type,
346 ) -> Option<&'ll Value> {
347 let volatile = if volatile { llvm::True } else { llvm::False };
348 let alignstack = if alignstack { llvm::True } else { llvm::False };
353 debug!("Asm Input Type: {:?}", *v);
356 .collect::<Vec<_>>();
358 debug!("Asm Output Type: {:?}", output);
359 let fty = bx.cx.type_func(&argtys[..], output);
361 // Ask LLVM to verify that the constraints are well-formed.
362 let constraints_ok = llvm::LLVMRustInlineAsmVerify(fty, cons.as_ptr().cast(), cons.len());
363 debug!("constraint verification result: {:?}", constraints_ok);
365 let v = llvm::LLVMRustInlineAsm(
369 cons.as_ptr().cast(),
373 llvm::AsmDialect::from_generic(dia),
375 let call = bx.call(v, inputs, None);
377 // Store mark in a metadata node so we can map LLVM errors
378 // back to source locations. See #17552.
380 let kind = llvm::LLVMGetMDKindIDInContext(
382 key.as_ptr() as *const c_char,
386 // srcloc contains one integer for each line of assembly code.
387 // Unfortunately this isn't enough to encode a full span so instead
388 // we just encode the start position of each line.
389 // FIXME: Figure out a way to pass the entire line spans.
390 let mut srcloc = vec![];
391 if dia == LlvmAsmDialect::Intel && line_spans.len() > 1 {
392 // LLVM inserts an extra line to add the ".intel_syntax", so add
393 // a dummy srcloc entry for it.
395 // Don't do this if we only have 1 line span since that may be
396 // due to the asm template string coming from a macro. LLVM will
397 // default to the first srcloc for lines that don't have an
398 // associated srcloc.
399 srcloc.push(bx.const_i32(0));
401 srcloc.extend(line_spans.iter().map(|span| bx.const_i32(span.lo().to_u32() as i32)));
402 let md = llvm::LLVMMDNodeInContext(bx.llcx, srcloc.as_ptr(), srcloc.len() as u32);
403 llvm::LLVMSetMetadata(call, kind, md);
407 // LLVM has detected an issue with our constraints, bail out
413 /// Converts a register class to an LLVM constraint code.
414 fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
416 InlineAsmRegOrRegClass::Reg(reg) => format!("{{{}}}", reg.name()),
417 InlineAsmRegOrRegClass::RegClass(reg) => match reg {
418 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r",
419 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w",
420 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
421 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
422 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => "l",
423 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
424 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
425 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => "t",
426 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16)
427 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8)
428 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
429 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
430 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
431 InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
432 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
433 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
434 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
435 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
436 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
437 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
438 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => "Q",
439 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => "q",
440 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
441 | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
442 InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
443 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
449 /// Converts a modifier into LLVM's equivalent modifier.
452 reg: InlineAsmRegClass,
453 modifier: Option<char>,
456 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier,
457 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
458 | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
459 if modifier == Some('v') { None } else { modifier }
461 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
462 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => None,
463 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
464 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,
465 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
466 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
467 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => Some('P'),
468 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
469 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
470 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
471 if modifier.is_none() {
477 InlineAsmRegClass::Hexagon(_) => None,
478 InlineAsmRegClass::Nvptx(_) => None,
479 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
480 | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
481 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
482 | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier {
483 None if arch == InlineAsmArch::X86_64 => Some('q'),
485 Some('l') => Some('b'),
486 Some('h') => Some('h'),
487 Some('x') => Some('w'),
488 Some('e') => Some('k'),
489 Some('r') => Some('q'),
492 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => None,
493 InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::xmm_reg)
494 | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::ymm_reg)
495 | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::zmm_reg) => match (reg, modifier) {
496 (X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
497 (X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
498 (X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
499 (_, Some('x')) => Some('x'),
500 (_, Some('y')) => Some('t'),
501 (_, Some('z')) => Some('g'),
504 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
508 /// Type to use for outputs that are discarded. It doesn't really matter what
509 /// the type is, as long as it is valid for the constraint code.
510 fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll Type {
512 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => cx.type_i32(),
513 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
514 | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
515 cx.type_vector(cx.type_i64(), 2)
517 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
518 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => cx.type_i32(),
519 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
520 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
521 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
522 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
523 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => cx.type_f64(),
524 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
525 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
526 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
527 cx.type_vector(cx.type_i64(), 2)
529 InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
530 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
531 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
532 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
533 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
534 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
535 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
536 | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => cx.type_i32(),
537 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => cx.type_i8(),
538 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
539 | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
540 | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
541 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
545 /// Helper function to get the LLVM type for a Scalar. Pointers are returned as
546 /// the equivalent integer type.
547 fn llvm_asm_scalar_type(cx: &CodegenCx<'ll, 'tcx>, scalar: &Scalar) -> &'ll Type {
549 Primitive::Int(Integer::I8, _) => cx.type_i8(),
550 Primitive::Int(Integer::I16, _) => cx.type_i16(),
551 Primitive::Int(Integer::I32, _) => cx.type_i32(),
552 Primitive::Int(Integer::I64, _) => cx.type_i64(),
553 Primitive::F32 => cx.type_f32(),
554 Primitive::F64 => cx.type_f64(),
555 Primitive::Pointer => cx.type_isize(),
560 /// Fix up an input value to work around LLVM bugs.
562 bx: &mut Builder<'a, 'll, 'tcx>,
563 mut value: &'ll Value,
564 reg: InlineAsmRegClass,
565 layout: &TyAndLayout<'tcx>,
567 match (reg, &layout.abi) {
568 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
569 if let Primitive::Int(Integer::I8, _) = s.value {
570 let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
571 bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
576 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
577 let elem_ty = llvm_asm_scalar_type(bx.cx, s);
578 let count = 16 / layout.size.bytes();
579 let vec_ty = bx.cx.type_vector(elem_ty, count);
580 if let Primitive::Pointer = s.value {
581 value = bx.ptrtoint(value, bx.cx.type_isize());
583 bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
586 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
587 Abi::Vector { element, count },
588 ) if layout.size.bytes() == 8 => {
589 let elem_ty = llvm_asm_scalar_type(bx.cx, element);
590 let vec_ty = bx.cx.type_vector(elem_ty, *count);
591 let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
592 bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
594 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
595 if s.value == Primitive::F64 =>
597 bx.bitcast(value, bx.cx.type_i64())
600 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
602 ) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
604 InlineAsmRegClass::Arm(
605 ArmInlineAsmRegClass::sreg_low16
606 | ArmInlineAsmRegClass::dreg_low8
607 | ArmInlineAsmRegClass::qreg_low4
608 | ArmInlineAsmRegClass::dreg
609 | ArmInlineAsmRegClass::qreg,
613 if let Primitive::Int(Integer::I32, _) = s.value {
614 bx.bitcast(value, bx.cx.type_f32())
623 /// Fix up an output value to work around LLVM bugs.
624 fn llvm_fixup_output(
625 bx: &mut Builder<'a, 'll, 'tcx>,
626 mut value: &'ll Value,
627 reg: InlineAsmRegClass,
628 layout: &TyAndLayout<'tcx>,
630 match (reg, &layout.abi) {
631 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
632 if let Primitive::Int(Integer::I8, _) = s.value {
633 bx.extract_element(value, bx.const_i32(0))
638 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
639 value = bx.extract_element(value, bx.const_i32(0));
640 if let Primitive::Pointer = s.value {
641 value = bx.inttoptr(value, layout.llvm_type(bx.cx));
646 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
647 Abi::Vector { element, count },
648 ) if layout.size.bytes() == 8 => {
649 let elem_ty = llvm_asm_scalar_type(bx.cx, element);
650 let vec_ty = bx.cx.type_vector(elem_ty, *count * 2);
651 let indices: Vec<_> = (0..*count).map(|x| bx.const_i32(x as i32)).collect();
652 bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
654 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
655 if s.value == Primitive::F64 =>
657 bx.bitcast(value, bx.cx.type_f64())
660 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
662 ) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
664 InlineAsmRegClass::Arm(
665 ArmInlineAsmRegClass::sreg_low16
666 | ArmInlineAsmRegClass::dreg_low8
667 | ArmInlineAsmRegClass::qreg_low4
668 | ArmInlineAsmRegClass::dreg
669 | ArmInlineAsmRegClass::qreg,
673 if let Primitive::Int(Integer::I32, _) = s.value {
674 bx.bitcast(value, bx.cx.type_i32())
683 /// Output type to use for llvm_fixup_output.
684 fn llvm_fixup_output_type(
685 cx: &CodegenCx<'ll, 'tcx>,
686 reg: InlineAsmRegClass,
687 layout: &TyAndLayout<'tcx>,
689 match (reg, &layout.abi) {
690 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
691 if let Primitive::Int(Integer::I8, _) = s.value {
692 cx.type_vector(cx.type_i8(), 8)
697 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
698 let elem_ty = llvm_asm_scalar_type(cx, s);
699 let count = 16 / layout.size.bytes();
700 cx.type_vector(elem_ty, count)
703 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
704 Abi::Vector { element, count },
705 ) if layout.size.bytes() == 8 => {
706 let elem_ty = llvm_asm_scalar_type(cx, element);
707 cx.type_vector(elem_ty, count * 2)
709 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
710 if s.value == Primitive::F64 =>
715 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
717 ) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
719 InlineAsmRegClass::Arm(
720 ArmInlineAsmRegClass::sreg_low16
721 | ArmInlineAsmRegClass::dreg_low8
722 | ArmInlineAsmRegClass::qreg_low4
723 | ArmInlineAsmRegClass::dreg
724 | ArmInlineAsmRegClass::qreg,
728 if let Primitive::Int(Integer::I32, _) = s.value {
734 _ => layout.llvm_type(cx),