1 //! Codegen of [`asm!`] invocations.
7 use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
8 use rustc_middle::mir::InlineAsmOperand;
9 use rustc_span::Symbol;
10 use rustc_target::asm::*;
12 pub(crate) fn codegen_inline_asm<'tcx>(
13 fx: &mut FunctionCx<'_, '_, 'tcx>,
15 template: &[InlineAsmTemplatePiece],
16 operands: &[InlineAsmOperand<'tcx>],
17 options: InlineAsmOptions,
19 // FIXME add .eh_frame unwind info directives
21 if template.is_empty() {
24 } else if template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string()) {
25 let true_ = fx.bcx.ins().iconst(types::I32, 1);
26 fx.bcx.ins().trapnz(true_, TrapCode::User(1));
28 } else if template[0] == InlineAsmTemplatePiece::String("movq %rbx, ".to_string())
31 InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
33 && template[2] == InlineAsmTemplatePiece::String("\n".to_string())
34 && template[3] == InlineAsmTemplatePiece::String("cpuid".to_string())
35 && template[4] == InlineAsmTemplatePiece::String("\n".to_string())
36 && template[5] == InlineAsmTemplatePiece::String("xchgq %rbx, ".to_string())
39 InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
42 assert_eq!(operands.len(), 4);
43 let (leaf, eax_place) = match operands[1] {
44 InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
47 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax))
50 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
51 crate::base::codegen_place(fx, out_place.unwrap()),
56 let ebx_place = match operands[0] {
57 InlineAsmOperand::Out { reg, late: true, place } => {
60 InlineAsmRegOrRegClass::RegClass(InlineAsmRegClass::X86(
61 X86InlineAsmRegClass::reg
64 crate::base::codegen_place(fx, place.unwrap())
68 let (sub_leaf, ecx_place) = match operands[2] {
69 InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
72 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx))
75 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
76 crate::base::codegen_place(fx, out_place.unwrap()),
81 let edx_place = match operands[3] {
82 InlineAsmOperand::Out { reg, late: true, place } => {
85 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx))
87 crate::base::codegen_place(fx, place.unwrap())
92 let (eax, ebx, ecx, edx) = crate::intrinsics::codegen_cpuid_call(fx, leaf, sub_leaf);
94 eax_place.write_cvalue(fx, CValue::by_val(eax, fx.layout_of(fx.tcx.types.u32)));
95 ebx_place.write_cvalue(fx, CValue::by_val(ebx, fx.layout_of(fx.tcx.types.u32)));
96 ecx_place.write_cvalue(fx, CValue::by_val(ecx, fx.layout_of(fx.tcx.types.u32)));
97 edx_place.write_cvalue(fx, CValue::by_val(edx, fx.layout_of(fx.tcx.types.u32)));
99 } else if fx.tcx.symbol_name(fx.instance).name.starts_with("___chkstk") {
100 // ___chkstk, ___chkstk_ms and __alloca are only used on Windows
101 crate::trap::trap_unimplemented(fx, "Stack probes are not supported");
102 } else if fx.tcx.symbol_name(fx.instance).name == "__alloca" {
103 crate::trap::trap_unimplemented(fx, "Alloca is not supported");
106 let mut inputs = Vec::new();
107 let mut outputs = Vec::new();
109 let mut asm_gen = InlineAssemblyGenerator {
111 arch: fx.tcx.sess.asm_arch.unwrap(),
115 registers: Vec::new(),
116 stack_slots_clobber: Vec::new(),
117 stack_slots_input: Vec::new(),
118 stack_slots_output: Vec::new(),
119 stack_slot_size: Size::from_bytes(0),
121 asm_gen.allocate_registers();
122 asm_gen.allocate_stack_slots();
124 let inline_asm_index = fx.cx.inline_asm_index.get();
125 fx.cx.inline_asm_index.set(inline_asm_index + 1);
127 format!("__inline_asm_{}_n{}", fx.cx.cgu_name.as_str().replace('.', "__").replace('-', "_"), inline_asm_index);
129 let generated_asm = asm_gen.generate_asm_wrapper(&asm_name);
130 fx.cx.global_asm.push_str(&generated_asm);
132 for (i, operand) in operands.iter().enumerate() {
134 InlineAsmOperand::In { reg: _, ref value } => {
136 asm_gen.stack_slots_input[i].unwrap(),
137 crate::base::codegen_operand(fx, value).load_scalar(fx),
140 InlineAsmOperand::Out { reg: _, late: _, place } => {
141 if let Some(place) = place {
143 asm_gen.stack_slots_output[i].unwrap(),
144 crate::base::codegen_place(fx, place),
148 InlineAsmOperand::InOut { reg: _, late: _, ref in_value, out_place } => {
150 asm_gen.stack_slots_input[i].unwrap(),
151 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
153 if let Some(out_place) = out_place {
155 asm_gen.stack_slots_output[i].unwrap(),
156 crate::base::codegen_place(fx, out_place),
160 InlineAsmOperand::Const { value: _ } => todo!(),
161 InlineAsmOperand::SymFn { value: _ } => todo!(),
162 InlineAsmOperand::SymStatic { def_id: _ } => todo!(),
166 call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
169 struct InlineAssemblyGenerator<'a, 'tcx> {
172 template: &'a [InlineAsmTemplatePiece],
173 operands: &'a [InlineAsmOperand<'tcx>],
174 options: InlineAsmOptions,
175 registers: Vec<Option<InlineAsmReg>>,
176 stack_slots_clobber: Vec<Option<Size>>,
177 stack_slots_input: Vec<Option<Size>>,
178 stack_slots_output: Vec<Option<Size>>,
179 stack_slot_size: Size,
182 impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
183 fn allocate_registers(&mut self) {
184 let sess = self.tcx.sess;
185 let map = allocatable_registers(
187 |feature| sess.target_features.contains(&Symbol::intern(feature)),
190 let mut allocated = FxHashMap::<_, (bool, bool)>::default();
191 let mut regs = vec![None; self.operands.len()];
193 // Add explicit registers to the allocated set.
194 for (i, operand) in self.operands.iter().enumerate() {
196 InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
198 allocated.entry(reg).or_default().0 = true;
200 InlineAsmOperand::Out {
201 reg: InlineAsmRegOrRegClass::Reg(reg), late: true, ..
204 allocated.entry(reg).or_default().1 = true;
206 InlineAsmOperand::Out { reg: InlineAsmRegOrRegClass::Reg(reg), .. }
207 | InlineAsmOperand::InOut { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
209 allocated.insert(reg, (true, true));
215 // Allocate out/inout/inlateout registers first because they are more constrained.
216 for (i, operand) in self.operands.iter().enumerate() {
218 InlineAsmOperand::Out {
219 reg: InlineAsmRegOrRegClass::RegClass(class),
223 | InlineAsmOperand::InOut {
224 reg: InlineAsmRegOrRegClass::RegClass(class), ..
226 let mut alloc_reg = None;
227 for ® in &map[&class] {
228 let mut used = false;
229 reg.overlapping_regs(|r| {
230 if allocated.contains_key(&r) {
236 alloc_reg = Some(reg);
241 let reg = alloc_reg.expect("cannot allocate registers");
243 allocated.insert(reg, (true, true));
249 // Allocate in/lateout.
250 for (i, operand) in self.operands.iter().enumerate() {
252 InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::RegClass(class), .. } => {
253 let mut alloc_reg = None;
254 for ® in &map[&class] {
255 let mut used = false;
256 reg.overlapping_regs(|r| {
257 if allocated.get(&r).copied().unwrap_or_default().0 {
263 alloc_reg = Some(reg);
268 let reg = alloc_reg.expect("cannot allocate registers");
270 allocated.entry(reg).or_default().0 = true;
272 InlineAsmOperand::Out {
273 reg: InlineAsmRegOrRegClass::RegClass(class),
277 let mut alloc_reg = None;
278 for ® in &map[&class] {
279 let mut used = false;
280 reg.overlapping_regs(|r| {
281 if allocated.get(&r).copied().unwrap_or_default().1 {
287 alloc_reg = Some(reg);
292 let reg = alloc_reg.expect("cannot allocate registers");
294 allocated.entry(reg).or_default().1 = true;
300 self.registers = regs;
303 fn allocate_stack_slots(&mut self) {
304 let mut slot_size = Size::from_bytes(0);
305 let mut slots_clobber = vec![None; self.operands.len()];
306 let mut slots_input = vec![None; self.operands.len()];
307 let mut slots_output = vec![None; self.operands.len()];
309 let new_slot_fn = |slot_size: &mut Size, reg_class: InlineAsmRegClass| {
311 reg_class.supported_types(self.arch).iter().map(|(ty, _)| ty.size()).max().unwrap();
312 let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
313 let offset = slot_size.align_to(align);
314 *slot_size = offset + reg_size;
317 let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
319 // Allocate stack slots for saving clobbered registers
321 InlineAsmClobberAbi::parse(self.arch, &self.tcx.sess.target, Symbol::intern("C"))
324 for (i, reg) in self.registers.iter().enumerate().filter_map(|(i, r)| r.map(|r| (i, r))) {
325 let mut need_save = true;
326 // If the register overlaps with a register clobbered by function call, then
327 // we don't need to save it.
328 for r in abi_clobber {
329 r.overlapping_regs(|r| {
341 slots_clobber[i] = Some(new_slot(reg.reg_class()));
345 // Allocate stack slots for inout
346 for (i, operand) in self.operands.iter().enumerate() {
348 InlineAsmOperand::InOut { reg, out_place: Some(_), .. } => {
349 let slot = new_slot(reg.reg_class());
350 slots_input[i] = Some(slot);
351 slots_output[i] = Some(slot);
357 let slot_size_before_input = slot_size;
358 let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
360 // Allocate stack slots for input
361 for (i, operand) in self.operands.iter().enumerate() {
363 InlineAsmOperand::In { reg, .. }
364 | InlineAsmOperand::InOut { reg, out_place: None, .. } => {
365 slots_input[i] = Some(new_slot(reg.reg_class()));
371 // Reset slot size to before input so that input and output operands can overlap
372 // and save some memory.
373 let slot_size_after_input = slot_size;
374 slot_size = slot_size_before_input;
375 let mut new_slot = |x| new_slot_fn(&mut slot_size, x);
377 // Allocate stack slots for output
378 for (i, operand) in self.operands.iter().enumerate() {
380 InlineAsmOperand::Out { reg, place: Some(_), .. } => {
381 slots_output[i] = Some(new_slot(reg.reg_class()));
387 slot_size = slot_size.max(slot_size_after_input);
389 self.stack_slots_clobber = slots_clobber;
390 self.stack_slots_input = slots_input;
391 self.stack_slots_output = slots_output;
392 self.stack_slot_size = slot_size;
395 fn generate_asm_wrapper(&self, asm_name: &str) -> String {
396 let mut generated_asm = String::new();
397 writeln!(generated_asm, ".globl {}", asm_name).unwrap();
398 writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
399 writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
400 writeln!(generated_asm, "{}:", asm_name).unwrap();
402 let is_x86 = matches!(self.arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
405 generated_asm.push_str(".intel_syntax noprefix\n");
407 Self::prologue(&mut generated_asm, self.arch);
409 // Save clobbered registers
410 if !self.options.contains(InlineAsmOptions::NORETURN) {
411 for (reg, slot) in self
414 .zip(self.stack_slots_clobber.iter().copied())
415 .filter_map(|(r, s)| r.zip(s))
417 Self::save_register(&mut generated_asm, self.arch, reg, slot);
421 // Write input registers
422 for (reg, slot) in self
425 .zip(self.stack_slots_input.iter().copied())
426 .filter_map(|(r, s)| r.zip(s))
428 Self::restore_register(&mut generated_asm, self.arch, reg, slot);
431 if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
432 generated_asm.push_str(".att_syntax\n");
435 // The actual inline asm
436 for piece in self.template {
438 InlineAsmTemplatePiece::String(s) => {
439 generated_asm.push_str(s);
441 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
442 if self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
443 generated_asm.push('%');
445 self.registers[*operand_idx]
447 .emit(&mut generated_asm, self.arch, *modifier)
452 generated_asm.push('\n');
454 if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
455 generated_asm.push_str(".intel_syntax noprefix\n");
458 if !self.options.contains(InlineAsmOptions::NORETURN) {
459 // Read output registers
460 for (reg, slot) in self
463 .zip(self.stack_slots_output.iter().copied())
464 .filter_map(|(r, s)| r.zip(s))
466 Self::save_register(&mut generated_asm, self.arch, reg, slot);
469 // Restore clobbered registers
470 for (reg, slot) in self
473 .zip(self.stack_slots_clobber.iter().copied())
474 .filter_map(|(r, s)| r.zip(s))
476 Self::restore_register(&mut generated_asm, self.arch, reg, slot);
479 Self::epilogue(&mut generated_asm, self.arch);
481 Self::epilogue_noreturn(&mut generated_asm, self.arch);
485 generated_asm.push_str(".att_syntax\n");
487 writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
488 generated_asm.push_str(".text\n");
489 generated_asm.push_str("\n\n");
494 fn prologue(generated_asm: &mut String, arch: InlineAsmArch) {
496 InlineAsmArch::X86 => {
497 generated_asm.push_str(" push ebp\n");
498 generated_asm.push_str(" mov ebp,[esp+8]\n");
500 InlineAsmArch::X86_64 => {
501 generated_asm.push_str(" push rbp\n");
502 generated_asm.push_str(" mov rbp,rdi\n");
504 InlineAsmArch::RiscV32 => {
505 generated_asm.push_str(" addi sp, sp, -8\n");
506 generated_asm.push_str(" sw ra, 4(sp)\n");
507 generated_asm.push_str(" sw s0, 0(sp)\n");
508 generated_asm.push_str(" mv s0, a0\n");
510 InlineAsmArch::RiscV64 => {
511 generated_asm.push_str(" addi sp, sp, -16\n");
512 generated_asm.push_str(" sd ra, 8(sp)\n");
513 generated_asm.push_str(" sd s0, 0(sp)\n");
514 generated_asm.push_str(" mv s0, a0\n");
516 _ => unimplemented!("prologue for {:?}", arch),
520 fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) {
522 InlineAsmArch::X86 => {
523 generated_asm.push_str(" pop ebp\n");
524 generated_asm.push_str(" ret\n");
526 InlineAsmArch::X86_64 => {
527 generated_asm.push_str(" pop rbp\n");
528 generated_asm.push_str(" ret\n");
530 InlineAsmArch::RiscV32 => {
531 generated_asm.push_str(" lw s0, 0(sp)\n");
532 generated_asm.push_str(" lw ra, 4(sp)\n");
533 generated_asm.push_str(" addi sp, sp, 8\n");
534 generated_asm.push_str(" ret\n");
536 InlineAsmArch::RiscV64 => {
537 generated_asm.push_str(" ld s0, 0(sp)\n");
538 generated_asm.push_str(" ld ra, 8(sp)\n");
539 generated_asm.push_str(" addi sp, sp, 16\n");
540 generated_asm.push_str(" ret\n");
542 _ => unimplemented!("epilogue for {:?}", arch),
546 fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) {
548 InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
549 generated_asm.push_str(" ud2\n");
551 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
552 generated_asm.push_str(" ebreak\n");
554 _ => unimplemented!("epilogue_noreturn for {:?}", arch),
559 generated_asm: &mut String,
565 InlineAsmArch::X86 => {
566 write!(generated_asm, " mov [ebp+0x{:x}], ", offset.bytes()).unwrap();
567 reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
568 generated_asm.push('\n');
570 InlineAsmArch::X86_64 => {
571 write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
572 reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
573 generated_asm.push('\n');
575 InlineAsmArch::RiscV32 => {
576 generated_asm.push_str(" sw ");
577 reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
578 writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
580 InlineAsmArch::RiscV64 => {
581 generated_asm.push_str(" sd ");
582 reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
583 writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
585 _ => unimplemented!("save_register for {:?}", arch),
590 generated_asm: &mut String,
596 InlineAsmArch::X86 => {
597 generated_asm.push_str(" mov ");
598 reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
599 writeln!(generated_asm, ", [ebp+0x{:x}]", offset.bytes()).unwrap();
601 InlineAsmArch::X86_64 => {
602 generated_asm.push_str(" mov ");
603 reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
604 writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
606 InlineAsmArch::RiscV32 => {
607 generated_asm.push_str(" lw ");
608 reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
609 writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
611 InlineAsmArch::RiscV64 => {
612 generated_asm.push_str(" ld ");
613 reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
614 writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
616 _ => unimplemented!("restore_register for {:?}", arch),
621 fn call_inline_asm<'tcx>(
622 fx: &mut FunctionCx<'_, '_, 'tcx>,
625 inputs: Vec<(Size, Value)>,
626 outputs: Vec<(Size, CPlace<'tcx>)>,
628 let stack_slot = fx.bcx.func.create_stack_slot(StackSlotData {
629 kind: StackSlotKind::ExplicitSlot,
630 size: u32::try_from(slot_size.bytes()).unwrap(),
632 if fx.clif_comments.enabled() {
633 fx.add_comment(stack_slot, "inline asm scratch slot");
636 let inline_asm_func = fx
642 call_conv: CallConv::SystemV,
643 params: vec![AbiParam::new(fx.pointer_type)],
648 let inline_asm_func = fx.module.declare_func_in_func(inline_asm_func, &mut fx.bcx.func);
649 if fx.clif_comments.enabled() {
650 fx.add_comment(inline_asm_func, asm_name);
653 for (offset, value) in inputs {
654 fx.bcx.ins().stack_store(value, stack_slot, i32::try_from(offset.bytes()).unwrap());
657 let stack_slot_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
658 fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
660 for (offset, place) in outputs {
661 let ty = fx.clif_type(place.layout().ty).unwrap();
662 let value = fx.bcx.ins().stack_load(ty, stack_slot, i32::try_from(offset.bytes()).unwrap());
663 place.write_cvalue(fx, CValue::by_val(value, place.layout()));