1 //! Codegen of [`asm!`] invocations.
7 use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
8 use rustc_middle::mir::InlineAsmOperand;
9 use rustc_span::Symbol;
10 use rustc_target::asm::*;
12 pub(crate) fn codegen_inline_asm<'tcx>(
13 fx: &mut FunctionCx<'_, '_, 'tcx>,
15 template: &[InlineAsmTemplatePiece],
16 operands: &[InlineAsmOperand<'tcx>],
17 options: InlineAsmOptions,
19 // FIXME add .eh_frame unwind info directives
21 if template.is_empty() {
24 } else if template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string()) {
25 let true_ = fx.bcx.ins().iconst(types::I32, 1);
26 fx.bcx.ins().trapnz(true_, TrapCode::User(1));
28 } else if template[0] == InlineAsmTemplatePiece::String("movq %rbx, ".to_string())
31 InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
33 && template[2] == InlineAsmTemplatePiece::String("\n".to_string())
34 && template[3] == InlineAsmTemplatePiece::String("cpuid".to_string())
35 && template[4] == InlineAsmTemplatePiece::String("\n".to_string())
36 && template[5] == InlineAsmTemplatePiece::String("xchgq %rbx, ".to_string())
39 InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: Some('r'), span: _ }
42 assert_eq!(operands.len(), 4);
43 let (leaf, eax_place) = match operands[1] {
44 InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
47 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax))
50 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
51 crate::base::codegen_place(fx, out_place.unwrap()),
56 let ebx_place = match operands[0] {
57 InlineAsmOperand::Out { reg, late: true, place } => {
60 InlineAsmRegOrRegClass::RegClass(InlineAsmRegClass::X86(
61 X86InlineAsmRegClass::reg
64 crate::base::codegen_place(fx, place.unwrap())
68 let (sub_leaf, ecx_place) = match operands[2] {
69 InlineAsmOperand::InOut { reg, late: true, ref in_value, out_place } => {
72 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx))
75 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
76 crate::base::codegen_place(fx, out_place.unwrap()),
81 let edx_place = match operands[3] {
82 InlineAsmOperand::Out { reg, late: true, place } => {
85 InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx))
87 crate::base::codegen_place(fx, place.unwrap())
92 let (eax, ebx, ecx, edx) = crate::intrinsics::codegen_cpuid_call(fx, leaf, sub_leaf);
94 eax_place.write_cvalue(fx, CValue::by_val(eax, fx.layout_of(fx.tcx.types.u32)));
95 ebx_place.write_cvalue(fx, CValue::by_val(ebx, fx.layout_of(fx.tcx.types.u32)));
96 ecx_place.write_cvalue(fx, CValue::by_val(ecx, fx.layout_of(fx.tcx.types.u32)));
97 edx_place.write_cvalue(fx, CValue::by_val(edx, fx.layout_of(fx.tcx.types.u32)));
99 } else if fx.tcx.symbol_name(fx.instance).name.starts_with("___chkstk") {
100 // ___chkstk, ___chkstk_ms and __alloca are only used on Windows
101 crate::trap::trap_unimplemented(fx, "Stack probes are not supported");
102 } else if fx.tcx.symbol_name(fx.instance).name == "__alloca" {
103 crate::trap::trap_unimplemented(fx, "Alloca is not supported");
106 let mut inputs = Vec::new();
107 let mut outputs = Vec::new();
109 let mut asm_gen = InlineAssemblyGenerator {
111 arch: InlineAsmArch::X86_64,
115 registers: Vec::new(),
116 stack_slots_clobber: Vec::new(),
117 stack_slots_input: Vec::new(),
118 stack_slots_output: Vec::new(),
119 stack_slot_size: Size::from_bytes(0),
121 asm_gen.allocate_registers();
122 asm_gen.allocate_stack_slots();
124 let inline_asm_index = fx.inline_asm_index;
125 fx.inline_asm_index += 1;
126 let asm_name = format!("{}__inline_asm_{}", fx.symbol_name, inline_asm_index);
128 let generated_asm = asm_gen.generate_asm_wrapper(&asm_name);
129 fx.cx.global_asm.push_str(&generated_asm);
131 // FIXME overlap input and output slots to save stack space
132 for (i, operand) in operands.iter().enumerate() {
134 InlineAsmOperand::In { reg: _, ref value } => {
136 asm_gen.stack_slots_input[i].unwrap(),
137 crate::base::codegen_operand(fx, value).load_scalar(fx),
140 InlineAsmOperand::Out { reg: _, late: _, place } => {
141 if let Some(place) = place {
143 asm_gen.stack_slots_output[i].unwrap(),
144 crate::base::codegen_place(fx, place),
148 InlineAsmOperand::InOut { reg: _, late: _, ref in_value, out_place } => {
150 asm_gen.stack_slots_input[i].unwrap(),
151 crate::base::codegen_operand(fx, in_value).load_scalar(fx),
153 if let Some(out_place) = out_place {
155 asm_gen.stack_slots_output[i].unwrap(),
156 crate::base::codegen_place(fx, out_place),
160 InlineAsmOperand::Const { value: _ } => todo!(),
161 InlineAsmOperand::SymFn { value: _ } => todo!(),
162 InlineAsmOperand::SymStatic { def_id: _ } => todo!(),
166 call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
169 struct InlineAssemblyGenerator<'a, 'tcx> {
172 template: &'a [InlineAsmTemplatePiece],
173 operands: &'a [InlineAsmOperand<'tcx>],
174 options: InlineAsmOptions,
175 registers: Vec<Option<InlineAsmReg>>,
176 stack_slots_clobber: Vec<Option<Size>>,
177 stack_slots_input: Vec<Option<Size>>,
178 stack_slots_output: Vec<Option<Size>>,
179 stack_slot_size: Size,
182 impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
183 fn allocate_registers(&mut self) {
184 let sess = self.tcx.sess;
185 let map = allocatable_registers(
187 |feature| sess.target_features.contains(&Symbol::intern(feature)),
190 let mut allocated = FxHashMap::<_, (bool, bool)>::default();
191 let mut regs = vec![None; self.operands.len()];
193 // Add explicit registers to the allocated set.
194 for (i, operand) in self.operands.iter().enumerate() {
196 InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
198 allocated.entry(reg).or_default().0 = true;
200 InlineAsmOperand::Out {
201 reg: InlineAsmRegOrRegClass::Reg(reg), late: true, ..
204 allocated.entry(reg).or_default().1 = true;
206 InlineAsmOperand::Out { reg: InlineAsmRegOrRegClass::Reg(reg), .. }
207 | InlineAsmOperand::InOut { reg: InlineAsmRegOrRegClass::Reg(reg), .. } => {
209 allocated.insert(reg, (true, true));
215 // Allocate out/inout/inlateout registers first because they are more constrained.
216 for (i, operand) in self.operands.iter().enumerate() {
218 InlineAsmOperand::Out {
219 reg: InlineAsmRegOrRegClass::RegClass(class),
223 | InlineAsmOperand::InOut {
224 reg: InlineAsmRegOrRegClass::RegClass(class), ..
226 let mut alloc_reg = None;
227 for ® in &map[&class] {
228 let mut used = false;
229 reg.overlapping_regs(|r| {
230 if allocated.contains_key(&r) {
236 alloc_reg = Some(reg);
241 let reg = alloc_reg.expect("cannot allocate registers");
243 allocated.insert(reg, (true, true));
249 // Allocate in/lateout.
250 for (i, operand) in self.operands.iter().enumerate() {
252 InlineAsmOperand::In { reg: InlineAsmRegOrRegClass::RegClass(class), .. } => {
253 let mut alloc_reg = None;
254 for ® in &map[&class] {
255 let mut used = false;
256 reg.overlapping_regs(|r| {
257 if allocated.get(&r).copied().unwrap_or_default().0 {
263 alloc_reg = Some(reg);
268 let reg = alloc_reg.expect("cannot allocate registers");
270 allocated.entry(reg).or_default().0 = true;
272 InlineAsmOperand::Out {
273 reg: InlineAsmRegOrRegClass::RegClass(class),
277 let mut alloc_reg = None;
278 for ® in &map[&class] {
279 let mut used = false;
280 reg.overlapping_regs(|r| {
281 if allocated.get(&r).copied().unwrap_or_default().1 {
287 alloc_reg = Some(reg);
292 let reg = alloc_reg.expect("cannot allocate registers");
294 allocated.entry(reg).or_default().1 = true;
300 self.registers = regs;
303 fn allocate_stack_slots(&mut self) {
304 let mut slot_size = Size::from_bytes(0);
305 let mut slots_clobber = vec![None; self.operands.len()];
306 let mut slots_input = vec![None; self.operands.len()];
307 let mut slots_output = vec![None; self.operands.len()];
309 let mut new_slot = |reg_class: InlineAsmRegClass| {
310 let reg_size = reg_class
311 .supported_types(InlineAsmArch::X86_64)
313 .map(|(ty, _)| ty.size())
316 let align = rustc_target::abi::Align::from_bytes(reg_size.bytes()).unwrap();
317 slot_size = slot_size.align_to(align);
318 let offset = slot_size;
319 slot_size += reg_size;
323 // Allocate stack slots for saving clobbered registers
325 InlineAsmClobberAbi::parse(self.arch, &self.tcx.sess.target, Symbol::intern("C"))
328 for (i, reg) in self.registers.iter().enumerate().filter_map(|(i, r)| r.map(|r| (i, r))) {
329 let mut need_save = true;
330 // If the register overlaps with a register clobbered by function call, then
331 // we don't need to save it.
332 for r in abi_clobber {
333 r.overlapping_regs(|r| {
345 slots_clobber[i] = Some(new_slot(reg.reg_class()));
349 // FIXME overlap input and output slots to save stack space
350 for (i, operand) in self.operands.iter().enumerate() {
352 InlineAsmOperand::In { reg, .. } => {
353 slots_input[i] = Some(new_slot(reg.reg_class()));
355 InlineAsmOperand::Out { reg, place, .. } => {
357 slots_output[i] = Some(new_slot(reg.reg_class()));
360 InlineAsmOperand::InOut { reg, out_place, .. } => {
361 let slot = new_slot(reg.reg_class());
362 slots_input[i] = Some(slot);
363 if out_place.is_some() {
364 slots_output[i] = Some(slot);
367 InlineAsmOperand::Const { value: _ } => (),
368 InlineAsmOperand::SymFn { value: _ } => (),
369 InlineAsmOperand::SymStatic { def_id: _ } => (),
373 self.stack_slots_clobber = slots_clobber;
374 self.stack_slots_input = slots_input;
375 self.stack_slots_output = slots_output;
376 self.stack_slot_size = slot_size;
379 fn generate_asm_wrapper(&self, asm_name: &str) -> String {
380 let mut generated_asm = String::new();
381 writeln!(generated_asm, ".globl {}", asm_name).unwrap();
382 writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
383 writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
384 writeln!(generated_asm, "{}:", asm_name).unwrap();
386 generated_asm.push_str(".intel_syntax noprefix\n");
387 generated_asm.push_str(" push rbp\n");
388 generated_asm.push_str(" mov rbp,rdi\n");
390 // Save clobbered registers
391 if !self.options.contains(InlineAsmOptions::NORETURN) {
392 for (reg, slot) in self
395 .zip(self.stack_slots_clobber.iter().copied())
396 .filter_map(|(r, s)| r.zip(s))
398 save_register(&mut generated_asm, self.arch, reg, slot);
402 // Write input registers
403 for (reg, slot) in self
406 .zip(self.stack_slots_input.iter().copied())
407 .filter_map(|(r, s)| r.zip(s))
409 restore_register(&mut generated_asm, self.arch, reg, slot);
412 if self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
413 generated_asm.push_str(".att_syntax\n");
416 // The actual inline asm
417 for piece in self.template {
419 InlineAsmTemplatePiece::String(s) => {
420 generated_asm.push_str(s);
422 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
423 self.registers[*operand_idx]
425 .emit(&mut generated_asm, self.arch, *modifier)
430 generated_asm.push('\n');
432 if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
433 generated_asm.push_str(".intel_syntax noprefix\n");
436 if !self.options.contains(InlineAsmOptions::NORETURN) {
437 // Read output registers
438 for (reg, slot) in self
441 .zip(self.stack_slots_output.iter().copied())
442 .filter_map(|(r, s)| r.zip(s))
444 save_register(&mut generated_asm, self.arch, reg, slot);
447 // Restore clobbered registers
448 for (reg, slot) in self
451 .zip(self.stack_slots_clobber.iter().copied())
452 .filter_map(|(r, s)| r.zip(s))
454 restore_register(&mut generated_asm, self.arch, reg, slot);
457 generated_asm.push_str(" pop rbp\n");
458 generated_asm.push_str(" ret\n");
460 generated_asm.push_str(" ud2\n");
463 generated_asm.push_str(".att_syntax\n");
464 writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
465 generated_asm.push_str(".text\n");
466 generated_asm.push_str("\n\n");
472 fn call_inline_asm<'tcx>(
473 fx: &mut FunctionCx<'_, '_, 'tcx>,
476 inputs: Vec<(Size, Value)>,
477 outputs: Vec<(Size, CPlace<'tcx>)>,
479 let stack_slot = fx.bcx.func.create_stack_slot(StackSlotData {
480 kind: StackSlotKind::ExplicitSlot,
481 size: u32::try_from(slot_size.bytes()).unwrap(),
483 if fx.clif_comments.enabled() {
484 fx.add_comment(stack_slot, "inline asm scratch slot");
487 let inline_asm_func = fx
493 call_conv: CallConv::SystemV,
494 params: vec![AbiParam::new(fx.pointer_type)],
499 let inline_asm_func = fx.module.declare_func_in_func(inline_asm_func, &mut fx.bcx.func);
500 if fx.clif_comments.enabled() {
501 fx.add_comment(inline_asm_func, asm_name);
504 for (offset, value) in inputs {
505 fx.bcx.ins().stack_store(value, stack_slot, i32::try_from(offset.bytes()).unwrap());
508 let stack_slot_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
509 fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
511 for (offset, place) in outputs {
512 let ty = fx.clif_type(place.layout().ty).unwrap();
513 let value = fx.bcx.ins().stack_load(ty, stack_slot, i32::try_from(offset.bytes()).unwrap());
514 place.write_cvalue(fx, CValue::by_val(value, place.layout()));
518 fn save_register(generated_asm: &mut String, arch: InlineAsmArch, reg: InlineAsmReg, offset: Size) {
520 InlineAsmArch::X86_64 => {
521 write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
522 reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
523 generated_asm.push('\n');
525 _ => unimplemented!("save_register for {:?}", arch),
530 generated_asm: &mut String,
536 InlineAsmArch::X86_64 => {
537 generated_asm.push_str(" mov ");
538 reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
539 writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
541 _ => unimplemented!("restore_register for {:?}", arch),