2 use crate::builder::Builder;
3 use crate::common::Funclet;
4 use crate::context::CodegenCx;
6 use crate::type_::Type;
7 use crate::type_of::LayoutLlvmExt;
8 use crate::value::Value;
10 use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece};
11 use rustc_codegen_ssa::mir::operand::OperandValue;
12 use rustc_codegen_ssa::traits::*;
13 use rustc_data_structures::fx::FxHashMap;
14 use rustc_middle::ty::layout::TyAndLayout;
15 use rustc_middle::{bug, span_bug, ty::Instance};
16 use rustc_span::{Pos, Span};
17 use rustc_target::abi::*;
18 use rustc_target::asm::*;
20 use libc::{c_char, c_uint};
21 use smallvec::SmallVec;
23 impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
24 fn codegen_inline_asm(
26 template: &[InlineAsmTemplatePiece],
27 operands: &[InlineAsmOperandRef<'tcx, Self>],
28 options: InlineAsmOptions,
30 instance: Instance<'_>,
31 dest_catch_funclet: Option<(Self::BasicBlock, Self::BasicBlock, Option<&Self::Funclet>)>,
33 let asm_arch = self.tcx.sess.asm_arch.unwrap();
35 // Collect the types of output operands
36 let mut constraints = vec![];
37 let mut clobbers = vec![];
38 let mut output_types = vec![];
39 let mut op_idx = FxHashMap::default();
40 let mut clobbered_x87 = false;
41 for (idx, op) in operands.iter().enumerate() {
43 InlineAsmOperandRef::Out { reg, late, place } => {
44 let is_target_supported = |reg_class: InlineAsmRegClass| {
45 for &(_, feature) in reg_class.supported_types(asm_arch) {
46 if let Some(feature) = feature {
47 let codegen_fn_attrs = self.tcx.codegen_fn_attrs(instance.def_id());
48 if self.tcx.sess.target_features.contains(&feature)
49 || codegen_fn_attrs.target_features.contains(&feature)
54 // Register class is unconditionally supported
61 let mut layout = None;
62 let ty = if let Some(ref place) = place {
63 layout = Some(&place.layout);
64 llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout)
67 InlineAsmRegClass::X86(
68 X86InlineAsmRegClass::mmx_reg | X86InlineAsmRegClass::x87_reg
71 // Special handling for x87/mmx registers: we always
72 // clobber the whole set if one register is marked as
73 // clobbered. This is due to the way LLVM handles the
74 // FP stack in inline assembly.
77 clobbers.push("~{st}".to_string());
79 clobbers.push(format!("~{{st({})}}", i));
83 } else if !is_target_supported(reg.reg_class())
84 || reg.reg_class().is_clobber_only(asm_arch)
86 // We turn discarded outputs into clobber constraints
87 // if the target feature needed by the register class is
88 // disabled. This is necessary otherwise LLVM will try
89 // to actually allocate a register for the dummy output.
90 assert!(matches!(reg, InlineAsmRegOrRegClass::Reg(_)));
91 clobbers.push(format!("~{}", reg_to_llvm(reg, None)));
94 // If the output is discarded, we don't really care what
95 // type is used. We're just using this to tell LLVM to
96 // reserve the register.
97 dummy_output_type(self.cx, reg.reg_class())
99 output_types.push(ty);
100 op_idx.insert(idx, constraints.len());
101 let prefix = if late { "=" } else { "=&" };
102 constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, layout)));
104 InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => {
105 let layout = if let Some(ref out_place) = out_place {
108 // LLVM required tied operands to have the same type,
109 // so we just use the type of the input.
112 let ty = llvm_fixup_output_type(self.cx, reg.reg_class(), layout);
113 output_types.push(ty);
114 op_idx.insert(idx, constraints.len());
115 let prefix = if late { "=" } else { "=&" };
116 constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, Some(layout))));
122 // Collect input operands
123 let mut inputs = vec![];
124 for (idx, op) in operands.iter().enumerate() {
126 InlineAsmOperandRef::In { reg, value } => {
128 llvm_fixup_input(self, value.immediate(), reg.reg_class(), &value.layout);
130 op_idx.insert(idx, constraints.len());
131 constraints.push(reg_to_llvm(reg, Some(&value.layout)));
133 InlineAsmOperandRef::InOut { reg, late: _, in_value, out_place: _ } => {
134 let value = llvm_fixup_input(
136 in_value.immediate(),
141 constraints.push(format!("{}", op_idx[&idx]));
143 InlineAsmOperandRef::SymFn { instance } => {
144 inputs.push(self.cx.get_fn(instance));
145 op_idx.insert(idx, constraints.len());
146 constraints.push("s".to_string());
148 InlineAsmOperandRef::SymStatic { def_id } => {
149 inputs.push(self.cx.get_static(def_id));
150 op_idx.insert(idx, constraints.len());
151 constraints.push("s".to_string());
157 // Build the template string
158 let mut template_str = String::new();
159 for piece in template {
161 InlineAsmTemplatePiece::String(ref s) => {
165 template_str.push_str("$$");
167 template_str.push(c);
171 template_str.push_str(s)
174 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
175 match operands[operand_idx] {
176 InlineAsmOperandRef::In { reg, .. }
177 | InlineAsmOperandRef::Out { reg, .. }
178 | InlineAsmOperandRef::InOut { reg, .. } => {
179 let modifier = modifier_to_llvm(asm_arch, reg.reg_class(), modifier);
180 if let Some(modifier) = modifier {
181 template_str.push_str(&format!(
183 op_idx[&operand_idx], modifier
186 template_str.push_str(&format!("${{{}}}", op_idx[&operand_idx]));
189 InlineAsmOperandRef::Const { ref string } => {
190 // Const operands get injected directly into the template
191 template_str.push_str(string);
193 InlineAsmOperandRef::SymFn { .. }
194 | InlineAsmOperandRef::SymStatic { .. } => {
195 // Only emit the raw symbol name
196 template_str.push_str(&format!("${{{}:c}}", op_idx[&operand_idx]));
203 constraints.append(&mut clobbers);
204 if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
206 InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
207 constraints.push("~{cc}".to_string());
209 InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
210 constraints.extend_from_slice(&[
211 "~{dirflag}".to_string(),
212 "~{fpsr}".to_string(),
213 "~{flags}".to_string(),
216 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
217 constraints.extend_from_slice(&[
218 "~{vtype}".to_string(),
220 "~{vxsat}".to_string(),
221 "~{vxrm}".to_string(),
224 InlineAsmArch::Avr => {
225 constraints.push("~{sreg}".to_string());
227 InlineAsmArch::Nvptx64 => {}
228 InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
229 InlineAsmArch::Hexagon => {}
230 InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
231 InlineAsmArch::S390x => {}
232 InlineAsmArch::SpirV => {}
233 InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {}
234 InlineAsmArch::Bpf => {}
235 InlineAsmArch::Msp430 => {
236 constraints.push("~{sr}".to_string());
240 if !options.contains(InlineAsmOptions::NOMEM) {
241 // This is actually ignored by LLVM, but it's probably best to keep
242 // it just in case. LLVM instead uses the ReadOnly/ReadNone
243 // attributes on the call instruction to optimize.
244 constraints.push("~{memory}".to_string());
246 let volatile = !options.contains(InlineAsmOptions::PURE);
247 let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
248 let output_type = match &output_types[..] {
249 [] => self.type_void(),
251 tys => self.type_struct(tys, false),
253 let dialect = match asm_arch {
254 InlineAsmArch::X86 | InlineAsmArch::X86_64
255 if !options.contains(InlineAsmOptions::ATT_SYNTAX) =>
257 llvm::AsmDialect::Intel
259 _ => llvm::AsmDialect::Att,
261 let result = inline_asm_call(
264 &constraints.join(","),
271 options.contains(InlineAsmOptions::MAY_UNWIND),
274 .unwrap_or_else(|| span_bug!(line_spans[0], "LLVM asm constraint validation failed"));
276 let mut attrs = SmallVec::<[_; 2]>::new();
277 if options.contains(InlineAsmOptions::PURE) {
278 if options.contains(InlineAsmOptions::NOMEM) {
279 attrs.push(llvm::AttributeKind::ReadNone.create_attr(self.cx.llcx));
280 } else if options.contains(InlineAsmOptions::READONLY) {
281 attrs.push(llvm::AttributeKind::ReadOnly.create_attr(self.cx.llcx));
283 attrs.push(llvm::AttributeKind::WillReturn.create_attr(self.cx.llcx));
284 } else if options.contains(InlineAsmOptions::NOMEM) {
285 attrs.push(llvm::AttributeKind::InaccessibleMemOnly.create_attr(self.cx.llcx));
287 // LLVM doesn't have an attribute to represent ReadOnly + SideEffect
289 attributes::apply_to_callsite(result, llvm::AttributePlace::Function, &{ attrs });
291 // Switch to the 'normal' basic block if we did an `invoke` instead of a `call`
292 if let Some((dest, _, _)) = dest_catch_funclet {
293 self.switch_to_block(dest);
296 // Write results to outputs
297 for (idx, op) in operands.iter().enumerate() {
298 if let InlineAsmOperandRef::Out { reg, place: Some(place), .. }
299 | InlineAsmOperandRef::InOut { reg, out_place: Some(place), .. } = *op
301 let value = if output_types.len() == 1 {
304 self.extract_value(result, op_idx[&idx] as u64)
306 let value = llvm_fixup_output(self, value, reg.reg_class(), &place.layout);
307 OperandValue::Immediate(value).store(self, place);
313 impl<'tcx> AsmMethods<'tcx> for CodegenCx<'_, 'tcx> {
314 fn codegen_global_asm(
316 template: &[InlineAsmTemplatePiece],
317 operands: &[GlobalAsmOperandRef<'tcx>],
318 options: InlineAsmOptions,
319 _line_spans: &[Span],
321 let asm_arch = self.tcx.sess.asm_arch.unwrap();
323 // Default to Intel syntax on x86
324 let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
325 && !options.contains(InlineAsmOptions::ATT_SYNTAX);
327 // Build the template string
328 let mut template_str = String::new();
330 template_str.push_str(".intel_syntax\n");
332 for piece in template {
334 InlineAsmTemplatePiece::String(ref s) => template_str.push_str(s),
335 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier: _, span: _ } => {
336 match operands[operand_idx] {
337 GlobalAsmOperandRef::Const { ref string } => {
338 // Const operands get injected directly into the
339 // template. Note that we don't need to escape $
340 // here unlike normal inline assembly.
341 template_str.push_str(string);
343 GlobalAsmOperandRef::SymFn { instance } => {
344 let llval = self.get_fn(instance);
345 self.add_compiler_used_global(llval);
346 let symbol = llvm::build_string(|s| unsafe {
347 llvm::LLVMRustGetMangledName(llval, s);
349 .expect("symbol is not valid UTF-8");
350 template_str.push_str(&symbol);
352 GlobalAsmOperandRef::SymStatic { def_id } => {
358 .unwrap_or_else(|| self.get_static(def_id));
359 self.add_compiler_used_global(llval);
360 let symbol = llvm::build_string(|s| unsafe {
361 llvm::LLVMRustGetMangledName(llval, s);
363 .expect("symbol is not valid UTF-8");
364 template_str.push_str(&symbol);
371 template_str.push_str("\n.att_syntax\n");
375 llvm::LLVMRustAppendModuleInlineAsm(
377 template_str.as_ptr().cast(),
384 pub(crate) fn inline_asm_call<'ll>(
385 bx: &mut Builder<'_, 'll, '_>,
388 inputs: &[&'ll Value],
389 output: &'ll llvm::Type,
392 dia: llvm::AsmDialect,
395 dest_catch_funclet: Option<(
396 &'ll llvm::BasicBlock,
397 &'ll llvm::BasicBlock,
398 Option<&Funclet<'ll>>,
400 ) -> Option<&'ll Value> {
401 let volatile = if volatile { llvm::True } else { llvm::False };
402 let alignstack = if alignstack { llvm::True } else { llvm::False };
403 let can_throw = if unwind { llvm::True } else { llvm::False };
408 debug!("Asm Input Type: {:?}", *v);
411 .collect::<Vec<_>>();
413 debug!("Asm Output Type: {:?}", output);
414 let fty = bx.cx.type_func(&argtys, output);
416 // Ask LLVM to verify that the constraints are well-formed.
417 let constraints_ok = llvm::LLVMRustInlineAsmVerify(fty, cons.as_ptr().cast(), cons.len());
418 debug!("constraint verification result: {:?}", constraints_ok);
420 let v = llvm::LLVMRustInlineAsm(
424 cons.as_ptr().cast(),
432 let call = if let Some((dest, catch, funclet)) = dest_catch_funclet {
433 bx.invoke(fty, None, v, inputs, dest, catch, funclet)
435 bx.call(fty, None, v, inputs, None)
438 // Store mark in a metadata node so we can map LLVM errors
439 // back to source locations. See #17552.
441 let kind = llvm::LLVMGetMDKindIDInContext(
443 key.as_ptr() as *const c_char,
447 // srcloc contains one integer for each line of assembly code.
448 // Unfortunately this isn't enough to encode a full span so instead
449 // we just encode the start position of each line.
450 // FIXME: Figure out a way to pass the entire line spans.
451 let mut srcloc = vec![];
452 if dia == llvm::AsmDialect::Intel && line_spans.len() > 1 {
453 // LLVM inserts an extra line to add the ".intel_syntax", so add
454 // a dummy srcloc entry for it.
456 // Don't do this if we only have 1 line span since that may be
457 // due to the asm template string coming from a macro. LLVM will
458 // default to the first srcloc for lines that don't have an
459 // associated srcloc.
460 srcloc.push(bx.const_i32(0));
462 srcloc.extend(line_spans.iter().map(|span| bx.const_i32(span.lo().to_u32() as i32)));
463 let md = llvm::LLVMMDNodeInContext(bx.llcx, srcloc.as_ptr(), srcloc.len() as u32);
464 llvm::LLVMSetMetadata(call, kind, md);
468 // LLVM has detected an issue with our constraints, bail out
474 /// If the register is an xmm/ymm/zmm register then return its index.
475 fn xmm_reg_index(reg: InlineAsmReg) -> Option<u32> {
477 InlineAsmReg::X86(reg)
478 if reg as u32 >= X86InlineAsmReg::xmm0 as u32
479 && reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
481 Some(reg as u32 - X86InlineAsmReg::xmm0 as u32)
483 InlineAsmReg::X86(reg)
484 if reg as u32 >= X86InlineAsmReg::ymm0 as u32
485 && reg as u32 <= X86InlineAsmReg::ymm15 as u32 =>
487 Some(reg as u32 - X86InlineAsmReg::ymm0 as u32)
489 InlineAsmReg::X86(reg)
490 if reg as u32 >= X86InlineAsmReg::zmm0 as u32
491 && reg as u32 <= X86InlineAsmReg::zmm31 as u32 =>
493 Some(reg as u32 - X86InlineAsmReg::zmm0 as u32)
499 /// If the register is an AArch64 vector register then return its index.
500 fn a64_vreg_index(reg: InlineAsmReg) -> Option<u32> {
502 InlineAsmReg::AArch64(reg)
503 if reg as u32 >= AArch64InlineAsmReg::v0 as u32
504 && reg as u32 <= AArch64InlineAsmReg::v31 as u32 =>
506 Some(reg as u32 - AArch64InlineAsmReg::v0 as u32)
512 /// Converts a register class to an LLVM constraint code.
513 fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) -> String {
515 // For vector registers LLVM wants the register name to match the type size.
516 InlineAsmRegOrRegClass::Reg(reg) => {
517 if let Some(idx) = xmm_reg_index(reg) {
518 let class = if let Some(layout) = layout {
519 match layout.size.bytes() {
525 // We use f32 as the type for discarded outputs
528 format!("{{{}mm{}}}", class, idx)
529 } else if let Some(idx) = a64_vreg_index(reg) {
530 let class = if let Some(layout) = layout {
531 match layout.size.bytes() {
536 1 => 'd', // We fixup i8 to i8x8
540 // We use i64x2 as the type for discarded outputs
543 format!("{{{}{}}}", class, idx)
544 } else if reg == InlineAsmReg::AArch64(AArch64InlineAsmReg::x30) {
545 // LLVM doesn't recognize x30
547 } else if reg == InlineAsmReg::Arm(ArmInlineAsmReg::r14) {
548 // LLVM doesn't recognize r14
551 format!("{{{}}}", reg.name())
554 // The constraints can be retrieved from
555 // https://llvm.org/docs/LangRef.html#supported-constraint-code-list
556 InlineAsmRegOrRegClass::RegClass(reg) => match reg {
557 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r",
558 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w",
559 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
560 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
561 unreachable!("clobber-only")
563 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
564 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
565 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
566 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => "t",
567 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16)
568 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8)
569 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
570 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
571 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
572 InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
573 InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
574 InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
575 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
576 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
577 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
578 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
579 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
580 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
581 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
582 | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
583 unreachable!("clobber-only")
585 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
586 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
587 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
588 unreachable!("clobber-only")
590 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
591 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => "Q",
592 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => "q",
593 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
594 | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
595 InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
596 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
597 InlineAsmRegClass::X86(
598 X86InlineAsmRegClass::x87_reg
599 | X86InlineAsmRegClass::mmx_reg
600 | X86InlineAsmRegClass::kreg0
601 | X86InlineAsmRegClass::tmm_reg,
602 ) => unreachable!("clobber-only"),
603 InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
604 InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
605 InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
606 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r",
607 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => "d",
608 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => "r",
609 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => "w",
610 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => "e",
611 InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r",
612 InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f",
613 InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => "r",
614 InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
615 bug!("LLVM backend does not support SPIR-V")
617 InlineAsmRegClass::Err => unreachable!(),
623 /// Converts a modifier into LLVM's equivalent modifier.
626 reg: InlineAsmRegClass,
627 modifier: Option<char>,
629 // The modifiers can be retrieved from
630 // https://llvm.org/docs/LangRef.html#asm-template-argument-modifiers
632 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier,
633 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
634 | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
635 if modifier == Some('v') { None } else { modifier }
637 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
638 unreachable!("clobber-only")
640 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None,
641 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
642 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,
643 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
644 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
645 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => Some('P'),
646 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
647 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
648 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
649 if modifier.is_none() {
655 InlineAsmRegClass::Hexagon(_) => None,
656 InlineAsmRegClass::Mips(_) => None,
657 InlineAsmRegClass::Nvptx(_) => None,
658 InlineAsmRegClass::PowerPC(_) => None,
659 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
660 | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
661 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
662 unreachable!("clobber-only")
664 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
665 | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier {
666 None if arch == InlineAsmArch::X86_64 => Some('q'),
668 Some('l') => Some('b'),
669 Some('h') => Some('h'),
670 Some('x') => Some('w'),
671 Some('e') => Some('k'),
672 Some('r') => Some('q'),
675 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => None,
676 InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::xmm_reg)
677 | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::ymm_reg)
678 | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::zmm_reg) => match (reg, modifier) {
679 (X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
680 (X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
681 (X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
682 (_, Some('x')) => Some('x'),
683 (_, Some('y')) => Some('t'),
684 (_, Some('z')) => Some('g'),
687 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
688 InlineAsmRegClass::X86(
689 X86InlineAsmRegClass::x87_reg
690 | X86InlineAsmRegClass::mmx_reg
691 | X86InlineAsmRegClass::kreg0
692 | X86InlineAsmRegClass::tmm_reg,
694 unreachable!("clobber-only")
696 InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None,
697 InlineAsmRegClass::Bpf(_) => None,
698 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair)
699 | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw)
700 | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => match modifier {
701 Some('h') => Some('B'),
702 Some('l') => Some('A'),
705 InlineAsmRegClass::Avr(_) => None,
706 InlineAsmRegClass::S390x(_) => None,
707 InlineAsmRegClass::Msp430(_) => None,
708 InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
709 bug!("LLVM backend does not support SPIR-V")
711 InlineAsmRegClass::Err => unreachable!(),
715 /// Type to use for outputs that are discarded. It doesn't really matter what
716 /// the type is, as long as it is valid for the constraint code.
717 fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'ll Type {
719 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => cx.type_i32(),
720 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
721 | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
722 cx.type_vector(cx.type_i64(), 2)
724 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
725 unreachable!("clobber-only")
727 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
728 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
729 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
730 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
731 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
732 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => cx.type_f64(),
733 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
734 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
735 | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
736 cx.type_vector(cx.type_i64(), 2)
738 InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
739 InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
740 InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
741 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
742 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
743 InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
744 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
745 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
746 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
747 InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
748 | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
749 unreachable!("clobber-only")
751 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
752 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
753 InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
754 unreachable!("clobber-only")
756 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
757 | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => cx.type_i32(),
758 InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => cx.type_i8(),
759 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
760 | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
761 | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
762 InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
763 InlineAsmRegClass::X86(
764 X86InlineAsmRegClass::x87_reg
765 | X86InlineAsmRegClass::mmx_reg
766 | X86InlineAsmRegClass::kreg0
767 | X86InlineAsmRegClass::tmm_reg,
769 unreachable!("clobber-only")
771 InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
772 InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
773 InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
774 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(),
775 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => cx.type_i8(),
776 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => cx.type_i16(),
777 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => cx.type_i16(),
778 InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => cx.type_i16(),
779 InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => cx.type_i32(),
780 InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => cx.type_f64(),
781 InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => cx.type_i16(),
782 InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
783 bug!("LLVM backend does not support SPIR-V")
785 InlineAsmRegClass::Err => unreachable!(),
789 /// Helper function to get the LLVM type for a Scalar. Pointers are returned as
790 /// the equivalent integer type.
791 fn llvm_asm_scalar_type<'ll>(cx: &CodegenCx<'ll, '_>, scalar: Scalar) -> &'ll Type {
792 match scalar.primitive() {
793 Primitive::Int(Integer::I8, _) => cx.type_i8(),
794 Primitive::Int(Integer::I16, _) => cx.type_i16(),
795 Primitive::Int(Integer::I32, _) => cx.type_i32(),
796 Primitive::Int(Integer::I64, _) => cx.type_i64(),
797 Primitive::F32 => cx.type_f32(),
798 Primitive::F64 => cx.type_f64(),
799 Primitive::Pointer => cx.type_isize(),
804 /// Fix up an input value to work around LLVM bugs.
805 fn llvm_fixup_input<'ll, 'tcx>(
806 bx: &mut Builder<'_, 'll, 'tcx>,
807 mut value: &'ll Value,
808 reg: InlineAsmRegClass,
809 layout: &TyAndLayout<'tcx>,
811 match (reg, layout.abi) {
812 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
813 if let Primitive::Int(Integer::I8, _) = s.primitive() {
814 let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
815 bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
820 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
821 let elem_ty = llvm_asm_scalar_type(bx.cx, s);
822 let count = 16 / layout.size.bytes();
823 let vec_ty = bx.cx.type_vector(elem_ty, count);
824 if let Primitive::Pointer = s.primitive() {
825 value = bx.ptrtoint(value, bx.cx.type_isize());
827 bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
830 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
831 Abi::Vector { element, count },
832 ) if layout.size.bytes() == 8 => {
833 let elem_ty = llvm_asm_scalar_type(bx.cx, element);
834 let vec_ty = bx.cx.type_vector(elem_ty, count);
835 let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
836 bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
838 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
839 if s.primitive() == Primitive::F64 =>
841 bx.bitcast(value, bx.cx.type_i64())
844 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
846 ) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
848 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
851 if let Primitive::Int(Integer::I32, _) = s.primitive() {
852 bx.bitcast(value, bx.cx.type_f32())
858 InlineAsmRegClass::Arm(
859 ArmInlineAsmRegClass::dreg
860 | ArmInlineAsmRegClass::dreg_low8
861 | ArmInlineAsmRegClass::dreg_low16,
865 if let Primitive::Int(Integer::I64, _) = s.primitive() {
866 bx.bitcast(value, bx.cx.type_f64())
871 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
872 match s.primitive() {
873 // MIPS only supports register-length arithmetics.
874 Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
875 Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
876 Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
884 /// Fix up an output value to work around LLVM bugs.
885 fn llvm_fixup_output<'ll, 'tcx>(
886 bx: &mut Builder<'_, 'll, 'tcx>,
887 mut value: &'ll Value,
888 reg: InlineAsmRegClass,
889 layout: &TyAndLayout<'tcx>,
891 match (reg, layout.abi) {
892 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
893 if let Primitive::Int(Integer::I8, _) = s.primitive() {
894 bx.extract_element(value, bx.const_i32(0))
899 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
900 value = bx.extract_element(value, bx.const_i32(0));
901 if let Primitive::Pointer = s.primitive() {
902 value = bx.inttoptr(value, layout.llvm_type(bx.cx));
907 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
908 Abi::Vector { element, count },
909 ) if layout.size.bytes() == 8 => {
910 let elem_ty = llvm_asm_scalar_type(bx.cx, element);
911 let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
912 let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
913 bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
915 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
916 if s.primitive() == Primitive::F64 =>
918 bx.bitcast(value, bx.cx.type_f64())
921 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
923 ) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
925 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
928 if let Primitive::Int(Integer::I32, _) = s.primitive() {
929 bx.bitcast(value, bx.cx.type_i32())
935 InlineAsmRegClass::Arm(
936 ArmInlineAsmRegClass::dreg
937 | ArmInlineAsmRegClass::dreg_low8
938 | ArmInlineAsmRegClass::dreg_low16,
942 if let Primitive::Int(Integer::I64, _) = s.primitive() {
943 bx.bitcast(value, bx.cx.type_i64())
948 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
949 match s.primitive() {
950 // MIPS only supports register-length arithmetics.
951 Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
952 Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
953 Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
954 Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
962 /// Output type to use for llvm_fixup_output.
963 fn llvm_fixup_output_type<'ll, 'tcx>(
964 cx: &CodegenCx<'ll, 'tcx>,
965 reg: InlineAsmRegClass,
966 layout: &TyAndLayout<'tcx>,
968 match (reg, layout.abi) {
969 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
970 if let Primitive::Int(Integer::I8, _) = s.primitive() {
971 cx.type_vector(cx.type_i8(), 8)
976 (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
977 let elem_ty = llvm_asm_scalar_type(cx, s);
978 let count = 16 / layout.size.bytes();
979 cx.type_vector(elem_ty, count)
982 InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
983 Abi::Vector { element, count },
984 ) if layout.size.bytes() == 8 => {
985 let elem_ty = llvm_asm_scalar_type(cx, element);
986 cx.type_vector(elem_ty, count * 2)
988 (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
989 if s.primitive() == Primitive::F64 =>
994 InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
996 ) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
998 InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
1001 if let Primitive::Int(Integer::I32, _) = s.primitive() {
1004 layout.llvm_type(cx)
1008 InlineAsmRegClass::Arm(
1009 ArmInlineAsmRegClass::dreg
1010 | ArmInlineAsmRegClass::dreg_low8
1011 | ArmInlineAsmRegClass::dreg_low16,
1015 if let Primitive::Int(Integer::I64, _) = s.primitive() {
1018 layout.llvm_type(cx)
1021 (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
1022 match s.primitive() {
1023 // MIPS only supports register-length arithmetics.
1024 Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
1025 Primitive::F32 => cx.type_i32(),
1026 Primitive::F64 => cx.type_i64(),
1027 _ => layout.llvm_type(cx),
1030 _ => layout.llvm_type(cx),