1 //! Emulate LLVM intrinsics
3 use crate::intrinsics::*;
6 use rustc_middle::ty::subst::SubstsRef;
8 pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
9 fx: &mut FunctionCx<'_, '_, 'tcx>,
11 _substs: SubstsRef<'tcx>,
12 args: &[mir::Operand<'tcx>],
14 target: Option<BasicBlock>,
17 // Used by `_mm_movemask_epi8` and `_mm256_movemask_epi8`
18 "llvm.x86.sse2.pmovmskb.128" | "llvm.x86.avx2.pmovmskb" | "llvm.x86.sse2.movmsk.pd" => {
19 intrinsic_args!(fx, args => (a); intrinsic);
21 let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
22 let lane_ty = fx.clif_type(lane_ty).unwrap();
23 assert!(lane_count <= 32);
25 let mut res = fx.bcx.ins().iconst(types::I32, 0);
27 for lane in (0..lane_count).rev() {
29 a.value_field(fx, mir::Field::new(lane.try_into().unwrap())).load_scalar(fx);
32 let a_lane = match lane_ty {
33 types::F32 => fx.bcx.ins().bitcast(types::I32, a_lane),
34 types::F64 => fx.bcx.ins().bitcast(types::I64, a_lane),
38 // extract sign bit of an int
39 let a_lane_sign = fx.bcx.ins().ushr_imm(a_lane, i64::from(lane_ty.bits() - 1));
41 // shift sign bit into result
42 let a_lane_sign = clif_intcast(fx, a_lane_sign, types::I32, false);
43 res = fx.bcx.ins().ishl_imm(res, 1);
44 res = fx.bcx.ins().bor(res, a_lane_sign);
47 let res = CValue::by_val(res, fx.layout_of(fx.tcx.types.i32));
48 ret.write_cvalue(fx, res);
50 "llvm.x86.sse2.cmp.ps" | "llvm.x86.sse2.cmp.pd" => {
51 let (x, y, kind) = match args {
52 [x, y, kind] => (x, y, kind),
53 _ => bug!("wrong number of args for intrinsic {intrinsic}"),
55 let x = codegen_operand(fx, x);
56 let y = codegen_operand(fx, y);
57 let kind = crate::constant::mir_operand_get_const_val(fx, kind)
58 .expect("llvm.x86.sse2.cmp.* kind not const");
60 let flt_cc = match kind
61 .try_to_bits(Size::from_bytes(1))
62 .unwrap_or_else(|| panic!("kind not scalar: {:?}", kind))
65 1 => FloatCC::LessThan,
66 2 => FloatCC::LessThanOrEqual,
67 7 => FloatCC::Ordered,
68 3 => FloatCC::Unordered,
69 4 => FloatCC::NotEqual,
70 5 => FloatCC::UnorderedOrGreaterThanOrEqual,
71 6 => FloatCC::UnorderedOrGreaterThan,
72 kind => unreachable!("kind {:?}", kind),
75 simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, res_lane_ty, x_lane, y_lane| {
76 let res_lane = match lane_ty.kind() {
77 ty::Float(_) => fx.bcx.ins().fcmp(flt_cc, x_lane, y_lane),
78 _ => unreachable!("{:?}", lane_ty),
80 bool_to_zero_or_max_uint(fx, res_lane_ty, res_lane)
83 "llvm.x86.sse2.psrli.d" => {
84 let (a, imm8) = match args {
85 [a, imm8] => (a, imm8),
86 _ => bug!("wrong number of args for intrinsic {intrinsic}"),
88 let a = codegen_operand(fx, a);
89 let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8)
90 .expect("llvm.x86.sse2.psrli.d imm8 not const");
92 simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| match imm8
93 .try_to_bits(Size::from_bytes(4))
94 .unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8))
96 imm8 if imm8 < 32 => fx.bcx.ins().ushr_imm(lane, i64::from(imm8 as u8)),
97 _ => fx.bcx.ins().iconst(types::I32, 0),
100 "llvm.x86.sse2.pslli.d" => {
101 let (a, imm8) = match args {
102 [a, imm8] => (a, imm8),
103 _ => bug!("wrong number of args for intrinsic {intrinsic}"),
105 let a = codegen_operand(fx, a);
106 let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8)
107 .expect("llvm.x86.sse2.psrli.d imm8 not const");
109 simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| match imm8
110 .try_to_bits(Size::from_bytes(4))
111 .unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8))
113 imm8 if imm8 < 32 => fx.bcx.ins().ishl_imm(lane, i64::from(imm8 as u8)),
114 _ => fx.bcx.ins().iconst(types::I32, 0),
117 "llvm.x86.sse2.storeu.dq" => {
118 intrinsic_args!(fx, args => (mem_addr, a); intrinsic);
119 let mem_addr = mem_addr.load_scalar(fx);
121 // FIXME correctly handle the unalignment
122 let dest = CPlace::for_ptr(Pointer::new(mem_addr), a.layout());
123 dest.write_cvalue(fx, a);
125 "llvm.x86.addcarry.64" => {
126 intrinsic_args!(fx, args => (c_in, a, b); intrinsic);
127 let c_in = c_in.load_scalar(fx);
129 llvm_add_sub(fx, BinOp::Add, ret, c_in, a, b);
131 "llvm.x86.subborrow.64" => {
132 intrinsic_args!(fx, args => (b_in, a, b); intrinsic);
133 let b_in = b_in.load_scalar(fx);
135 llvm_add_sub(fx, BinOp::Sub, ret, b_in, a, b);
140 .warn(&format!("unsupported llvm intrinsic {}; replacing with trap", intrinsic));
141 crate::trap::trap_unimplemented(fx, intrinsic);
145 let dest = target.expect("all llvm intrinsics used by stdlib should return");
146 let ret_block = fx.get_block(dest);
147 fx.bcx.ins().jump(ret_block, &[]);
150 // llvm.x86.avx2.vperm2i128
151 // llvm.x86.ssse3.pshuf.b.128
152 // llvm.x86.avx2.pshuf.b
153 // llvm.x86.avx2.psrli.w
154 // llvm.x86.sse2.psrli.w
156 fn llvm_add_sub<'tcx>(
157 fx: &mut FunctionCx<'_, '_, 'tcx>,
167 "llvm.x86.addcarry.64/llvm.x86.subborrow.64 second operand must be u64"
172 "llvm.x86.addcarry.64/llvm.x86.subborrow.64 third operand must be u64"
175 // c + carry -> c + first intermediate carry or borrow respectively
176 let int0 = crate::num::codegen_checked_int_binop(fx, bin_op, a, b);
177 let c = int0.value_field(fx, mir::Field::new(0));
178 let cb0 = int0.value_field(fx, mir::Field::new(1)).load_scalar(fx);
180 // c + carry -> c + second intermediate carry or borrow respectively
181 let cb_in_as_u64 = fx.bcx.ins().uextend(types::I64, cb_in);
182 let cb_in_as_u64 = CValue::by_val(cb_in_as_u64, fx.layout_of(fx.tcx.types.u64));
183 let int1 = crate::num::codegen_checked_int_binop(fx, bin_op, c, cb_in_as_u64);
184 let (c, cb1) = int1.load_scalar_pair(fx);
186 // carry0 | carry1 -> carry or borrow respectively
187 let cb_out = fx.bcx.ins().bor(cb0, cb1);
189 let layout = fx.layout_of(fx.tcx.mk_tup([fx.tcx.types.u8, fx.tcx.types.u64].iter()));
190 let val = CValue::by_val_pair(cb_out, c, layout);
191 ret.write_cvalue(fx, val);